Datasheet

Data Sheet ADP1872/ADP1873
Rev. B | Page 27 of 40
THERMAL CONSIDERATIONS
The ADP1872/ADP1873 are used for dc-to-dc, step down, high
current applications that have an on-board controller and on-board
MOSFET drivers. Because applications may require up to 20 A of
load current delivery and be subjected to high ambient temperature
surroundings, the selection of external upper side and lower side
MOSFETs must be associated with careful thermal consideration
to not exceed the maximum allowable junction temperature
of 125°C. To avoid permanent or irreparable damage if the
junction temperature reaches or exceeds 155°C, the part enters
thermal shutdown, turning off both external MOSFETs, and
does not re-enable until the junction temperature cools to 140°C
(see the Thermal Shutdown section).
The maximum junction temperature allowed for the ADP1872/
ADP1873 ICs is 125°C. This means that the sum of the ambient
temperature (T
A
) and the rise in package temperature (T
R
), which
is caused by the thermal impedance of the package and the internal
power dissipation, should not exceed 125°C, as dictated by
T
J
= T
R
× T
A
where:
T
J
is the maximum junction temperature.
T
R
is the rise in package temperature due to the power
dissipated from within.
T
A
is the ambient temperature.
The rise in package temperature is directly proportional to its
thermal impedance characteristics. The following equation
represents this proportionality relationship:
T
R
= θ
JA
× P
DR (LOSS)
where:
θ
JA
is the thermal resistance of the package from the junction to
the outside surface of the die, where it meets the surrounding air.
P
DR (LOSS)
is the overall power dissipated by the IC.
The bulk of the power dissipated is due to the gate capacitance
of the external MOSFETs. The power loss equation of the
MOSFET drivers (see the MOSFET Driver Loss section in the
Efficiency Consideration section) is
P
DR (LOSS)
= [V
DR
× (f
SW
C
upperFET
V
DR
+ I
BIAS
)] + [V
DD
×
(f
SW
C
lowerFET
V
DD
+ I
BIAS
)]
where:
C
upperFET
is the input gate capacitance of the upper side MOSFET.
C
lowerFET
is the input gate capacitance of the lower side MOSFET.
I
BIAS
is the dc current (2 mA) flowing into the upper side and
lower side drivers.
V
DR
is the driver bias voltage (that is, the low input voltage (V
DD
)
minus the rectifier drop (see Figure 80)).
V
DD
is the bias voltage
For example, if the external MOSFET characteristics are θ
JA
(10-lead MSOP) = 171.2°C/W, f
SW
= 300 kHz, I
BIAS
= 2 mA,
C
upperFET
= 3.3 nF, C
lowerFET
= 3.3 nF, V
DR
= 5.12 V, and V
DD
= 5 . 5 V,
then the power loss is
P
DR (LOSS)
= [V
DR
× (f
SW
C
upperFET
V
DR
+ I
BIAS
)] + [V
DD
×
(f
SW
C
lowerFET
V
DD
+ I
BIAS
)]
= [5.12 × (300 × 10
3
× 3.3 × 10
−9
× 5.12 + 0.002)] +
[5.5 × (300 × 10
3
×3.3 × 10
−9
× 5.5 + 0.002)]
= 77.13 mW
The rise in package temperature is
T
R
= θ
JA
× P
DR (LOSS)
= 171.2°C × 77.13 mW
= 13.2°C
Assuming a maximum ambient temperature environment of 85°C,
the junction temperature is
T
J
= T
R
× T
A
= 13.2°C + 85°C = 98.2°C
which is below the maximum junction temperature of 125°C.
DESIGN EXAMPLE
The ADP1872/ADP1873 are easy to use, requiring only a few
design criteria. For example, the example outlined in this section
uses only four design criteria: V
OUT
= 1.8 V, I
LOAD
= 15 A (pulsing),
VIN = 12 V (typical), and f
SW
= 300 kHz.
Input Capacitor
The maximum input voltage ripple is usually 1% of the
minimum input voltage (11.8 V × 0.01 = 120 mV).
V
RIPP
= 120 mV
V
MAX, RIPPLE
= V
RIPP
− (I
LOAD, MAX
× ESR)
= 120 mV − (15 A × 0.001) = 45 mV
mV105103004
A15
4
3
,
,
×××
==
RIPPLEMAXSW
MAXLOAD
minIN,
Vf
I
C
= 120 µF
Choose five 22 µF ceramic capacitors. The overall ESR of five
22 µF ceramic capacitors is less than 1 mΩ.
I
RMS
= I
LOAD
/2 = 7.5 A
P
CIN
= (I
RMS
)
2
× ESR = (7.5A)
2
× 1 mΩ = 56.25 mW
Inductor
Determining inductor ripple current amplitude:
3
LOAD
L
I
I ≈∆
= 5 A
so calculating for the inductor value
V2.13
V8.1
10300V5
)V8.1V2.13(
)(
3
,
×
××
−
=
×
×∆
−
=
MAXIN,
OUT
SW
L
OUT
MAXIN
V
V
fI
VV
L
= 1.03 µH