Datasheet

ADP1872/ADP1873 Data Sheet
Rev. B | Page 26 of 40
Body Diode Conduction Loss
The ADP1872/ADP1873 employ anticross conduction circuitry
that prevents the upper side and lower side MOSFETs from
conducting current simultaneously. This overlap control is
beneficial, avoiding large current flow that may lead to
irreparable damage to the external components of the power
stage. However, this blanking period comes with the trade-off of
a diode conduction loss occurring immediately after the
MOSFETs change states and continuing well into idle mode.
The amount of loss through the body diode of the lower side
MOSFET during the antioverlap state is given by
2
)(
)(

F
LOAD
SW
LOSSBODY
LOSSBODY
VI
t
t
P
where:
t
BODY (LOSS)
is the body conduction time (refer to Figure 81 for
dead time periods).
t
SW
is the period per switching cycle.
V
F
is the forward drop of the body diode during conduction.
(Refer to the selected external MOSFET data sheet for more
information about the V
F
parameter.)
80
72
64
56
48
40
32
24
16
8
2.7 5.54.84.13.4
BODY DIODE CONDUCTION TIME (ns)
V
DD
(V)
+125°C
+25°C
–40°C
1MHz
300kHz
08297-080
Figure 81. Body Diode Conduction Time vs. Low Voltage Input (V
DD
)
Inductor Loss
During normal conduction mode, further power loss is caused
by the conduction of current through the inductor windings,
which have dc resistance (DCR). Typically, larger sized inductors
have smaller DCR values.
The inductor core loss is a result of the eddy currents generated
within the core material. These eddy currents are induced by the
changing flux, which is produced by the current flowing through
the windings. The amount of inductor core loss depends on the
core material, the flux swing, the frequency, and the core volume.
Ferrite inductors have the lowest core losses, whereas powdered iron
inductors have higher core losses. It is recommended to use shielded
ferrite core material type inductors with the ADP1872/ADP1873
for a high current, dc-to-dc switching application to achieve
minimal loss and negligible electromagnetic interference (EMI).
P
DCR (LOSS)
= DCR ×
2
LOAD
I
+ Core Loss
INPUT CAPACITOR SELECTION
The goal in selecting an input capacitor is to reduce or to minimize
input voltage ripple and to reduce the high frequency source
impedance, which is essential for achieving predictable loop
stability and transient performance.
The problem with using bulk capacitors, other than their physical
geometries, is their large equivalent series resistance (ESR) and
large equivalent series inductance (ESL). Aluminum electrolytic
capacitors have such high ESR that they cause undesired input
voltage ripple magnitudes and are generally not effective at high
switching frequencies.
If bulk capacitors are to be used, it is recommended to use multi-
layered ceramic capacitors (MLCC) in parallel due to their low
ESR values. This dramatically reduces the input voltage ripple
amplitude as long as the MLCCs are mounted directly across
the drain of the upper side MOSFET and the source terminal of
the lower side MOSFET (see the Layout Considerations section).
Improper placement and mounting of these MLCCs may cancel
their effectiveness due to stray inductance and an increase in
trace impedance.

OUT
OUTOUT
MAXLOADRMSCIN
V
VVINV
II


,,
The maximum input voltage ripple and maximum input capacitor
rms current occur at the end of the duration of 1 − D while the
upper side MOSFET is in the off state. The input capacitor rms
current reaches its maximum at time D. When calculating the
maximum input voltage ripple, account for the ESR of the input
capacitor as follows:
V
MAX, RIPPLE
= V
RIPP
+ (I
LOAD, MAX
× ESR)
where:
V
RIPP
is usually 1% of the minimum voltage input.
I
LOAD, MAX
is the maximum load current.
ESR is the equivalent series resistance rating of the input
capacitor used.
Inserting V
MAX, RIPPLE
into the charge balance equation to calculate
the minimum input capacitor requirement gives
SWRIPPLEMAX
MAXLOAD
minIN,
f
DD
V
I
C
)1(
,
,


or
RIPPLEMAXSW
MAXLOAD
minIN,
Vf
I
C
,
,
4

where D = 50%.