Datasheet
Data Sheet ADP1872/ADP1873
Rev. B | Page 25 of 40
EFFICIENCY CONSIDERATION
One of the important criteria to consider in constructing a dc-to-dc
converter is efficiency. By definition, efficiency is the ratio of the
output power to the input power. For high power applications at
load currents up to 20 A, the following are important MOSFET
parameters that aid in the selection process:
V
GS (TH)
: the MOSFET support voltage applied between the
gate and the source.
R
DS (ON)
: the MOSFET on resistance during channel
conduction.
Q
G
: the total gate charge
C
N1
: the input capacitance of the upper side switch
C
N2
: the input capacitance of the lower side switch
The following are the losses experienced through the external
component during normal switching operation:
Channel conduction loss (both the MOSFETs)
MOSFET driver loss
MOSFET switching loss
Body diode conduction loss (lower side MOSFET)
Inductor loss (copper and core loss)
Channel Conduction Loss
During normal operation, the bulk of the loss in efficiency is due
to the power dissipated through MOSFET channel conduction.
Power loss through the upper side MOSFET is directly proportional
to the duty cycle (D) for each switching period, and the power
loss through the lower side MOSFET is directly proportional to
1 − D for each switching period. The selection of MOSFETs is
governed by the amount of maximum dc load current that the
converter is expected to deliver. In particular, the selection of
the lower side MOSFET is dictated by the maximum load
current because a typical high current application employs duty
cycles of less than 50%. Therefore, the lower side MOSFET is in
the on state for most of the switching period.
P
N1, N2 (CL)
= [D × R
N1 (ON)
+ (1 − D) × R
N2 (ON)
] ×
2
LOAD
I
MOSFET Driver Loss
Other dissipative elements are the MOSFET drivers. The
contributing factors are the dc current flowing through the
driver during operation and the Q
GATE
parameter of the external
MOSFETs.
BIAS
DD
lowerFET
SW
DD
BIAS
DR
upperFET
SW
DR
LOSSDR
IVCfV
IVCfVP
)(
where:
C
upperFET
is the input gate capacitance of the upper-side MOSFET.
C
lowerFET
is the input gate capacitance of the lower-side MOSFET.
V
DR
is the driver bias voltage (that is, the low input voltage (V
DD
)
minus the rectifier drop (see Figure 80)).
I
BIAS
is the dc current flowing into the upper- and lower-side drivers.
V
DD
is the bias voltage.
800
720
640
560
480
400
320
240
160
80
300 1000900800700600500400
RECTIFIER DROP (mV)
FREQUENCY (kHz)
+125°C
+25°C
–40°C
V
DD
= 2.7V
V
DD
= 3.6V
V
DD
= 5.5V
08297-079
Figure 80. Internal Rectifier Voltage Drop vs. Switching Frequency
MOSFET Switching Loss
The SW node transitions due to the switching activities of the
upper side and lower side MOSFETs. This causes removal and
replenishing of charge to and from the gate oxide layer of the
MOSFET, as well as to and from the parasitic capacitance
associated with the gate oxide edge overlap and the drain and
source terminals. The current that enters and exits these charge
paths presents additional loss during these transition times.
This can be approximately quantified by using the following
equation, which represents the time in which charge enters and
exits these capacitive regions.
t
SW-TRANS
= R
GATE
× C
TOTAL
where:
R
GATE
is the gate input resistance of the MOSFET.
C
TOTAL
is the C
GD
+ C
GS
of the external MOSFET used.
The ratio of this time constant to the period of one switching cycle
is the multiplying factor to be used in the following expression:
2
-
)(
VINI
t
t
P
LOAD
SW
TRANSSW
LOSSSW
or
P
SW (LOSS)
= f
SW
× R
GATE
× C
TOTAL
× I
LOAD
× VIN × 2