Datasheet

ManualsBrandsANALOG DEVICES ManualsPMICsPMIC - voltage regulators - DC DC switch controllers MSOP 10

Synchronous Current-Mode with

Constant On-Time, PWM Buck Controller

Data Sheet

ADP1872/ADP1873

Rev. B

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FEATURES

Power input voltage as low as 2.75 V to 20 V

Bias supply voltage range: 2.75 V to 5.5 V

Minimum output voltage: 0.6 V

0.6 V reference voltage with ±1.0% accuracy

Supports all N-channel MOSFET power stages

Available in 300 kHz, 600 KHz, and 1.0 MHz options

No current-sense resistor required

Power saving mode (PSM) for light loads (ADP1873 only)

Resistor-programmable current-sense gain

Thermal overload protection

Short-circuit protection

Precision enable input

Integrated bootstrap diode for high-side drive

140 µA shutdown supply current

Starts into a precharged load

Small, 10-lead MSOP package

APPLICATIONS

Telecom and networking systems

Mid to high end servers

Set-top boxes

DSP core power supplies

TYPICAL APPLICATIONS CIRCUIT

COMP/EN

BST

DRVH

GND

VDD

DRVL

PGND

VIN

VDD

VDD2

TOP

BOT

OUT

= 2.75V

TO 5.5V

RES

OUT

BST

LOAD

= 2.75V TO 20V

ADP1872/

ADP1873

08297-001

Figure 1.

100

100 1k 10k 100k

EFFICIENCY (%)

LOAD CURRENT (mA)

= 5.5V, V

= 5.5V (PSM)

= 5.5V, V

= 16.5V (PSM)

= 5.5V, V

= 13.0V (PSM)

= 5.5V, V

= 5.5V

= 25°C

OUT

= 1.8V

= 300kHz

WURTH INDUCTOR:

744325120, L = 1.2µH, DCR = 1.8mΩ

INFINEON FETs:

BSC042N03MS G (UPPER/LOWER)

08297-002

Figure 2. ADP1872 Efficiency vs. Load Current (V

OUT

= 1.8 V, 300 kHz)

GENERAL DESCRIPTION

The ADP1872/ADP1873 are versatile current-mode, synchronous

step-down controllers that provide superior transient response,

optimal stability, and current limit protection by using a constant

on-time, pseudo-fixed frequency with a programmable current-

sense gain, current-control scheme. In addition, these devices offer

optimum performance at low duty cycles by using valley current-

mode control architecture. This allows the ADP1872/ADP1873

to drive all N-channel power stages to regulate output voltages

as low as 0.6 V.

The ADP1873 is the power saving mode (PSM) version of the

device and is capable of pulse skipping to maintain output

regulation while achieving improved system efficiency at light

loads (see the Power Saving Mode (PSM) Version (ADP1873)

section for more information).

Available in three frequency options (300 kHz, 600 kHz, and

1.0 MHz, plus the PSM option), the ADP1872/ADP1873 are

well suited for a wide range of applications. These ICs not only

operate from a 2.75 V to 5.5 V bias supply, but can also accept a

power input as high as 20 V.

In addition, an internally fixed, soft start period is included to limit

input in-rush current from the input supply during startup and

to provide reverse current protection during soft start for a pre-

charged output. The low-side current-sense, current-gain scheme

and integration of a boost diode, along with the PSM/forced pulse-

width modulation (PWM) option, reduce the external part count

and improve efficiency.

The ADP1872/ADP1873 operate over the −40°C to +125°C

junction temperature range and are available in a 10-lead MSOP.

Summary of content (40 pages)

PAGE 1
Synchronous Current-Mode with Constant On-Time, PWM Buck Controller ADP1872/ADP1873 Data Sheet FEATURES TYPICAL APPLICATIONS CIRCUIT VIN = 2.75V TO 20V ADP1872/ ADP1873 BST COMP/EN VOUT CIN CBST RTOP FB DRVH RBOT CVDD2 VDD = 2.75V TO 5.5V GND SW VDD DRVL PGND Q1 L VOUT COUT Q2 RRES + LOAD 5A CVDD Figure 1. 100 VDD = 5.5V, VIN = 5.5V (PSM) VDD = 5.5V, VIN = 5.5V 95 90 85 VDD = 5.5V, VIN = 13.0V (PSM) 80 75 70 VDD = 5.5V, VIN = 16.5V (PSM) 65 TA = 25°C VOUT = 1.
PAGE 2
ADP1872/ADP1873 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Timer Operation ........................................................................ 21 Applications ....................................................................................... 1 Pseudo-Fixed Frequency ........................................................... 22 Typical Applications Circuit..............................................
PAGE 3
Data Sheet ADP1872/ADP1873 SPECIFICATIONS All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). VDD = 5 V, BST − SW = 5 V, VIN = 13 V. The specifications are valid for TJ = −40°C to +125°C, unless otherwise specified. Table 1.
PAGE 4
ADP1872/ADP1873 Data Sheet Parameter OUTPUT DRIVER CHARACTERISTICS High-Side Driver Output Source Resistance Output Sink Resistance Rise Time 2 Fall Time2 Low-Side Driver Output Source Resistance Output Sink Resistance Rise Time2 Fall Time2 Propagation Delays DRVL Fall to DRVH Rise2 DRVH Fall to DRVL Rise2 SW Leakage Current Integrated Rectifier Channel Impedance PRECISION ENABLE THRESHOLD Logic High Level Enable Hysteresis COMP VOLTAGE COMP Clamp Low Voltage Symbol Conditions COMP Clamp High Voltage C
PAGE 5
Data Sheet ADP1872/ADP1873 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings apply individually only, not in combination. Unless otherwise specified, all other voltages are referenced to PGND. Table 2. Parameter VDD to GND VIN to PGND FB, COMP/EN to GND DRVL to PGND SW to PGND SW to PGND BST to SW BST to PGND DRVH to SW PGND to GND Operating Junction Temperature Range Storage Temperature Range Soldering Conditions Maximum Soldering Lead Temperature (10 sec) Rating −0.3 V to +6 V −0.3 V to +28 V −0.
PAGE 6
ADP1872/ADP1873 Data Sheet VIN 1 COMP/EN 2 FB 3 GND 4 VDD 5 10 BST ADP1872 9 SW TOP VIEW (Not to Scale) 8 DRVH 7 PGND 6 DRVL 08297-003 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 3 4 Mnemonic VIN COMP/EN FB GND 5 VDD 6 DRVL 7 8 9 10 PGND DRVH SW BST Description High Input Voltage. Connect VIN to the drain of the upper-side MOSFET. Output of the Internal Error Amplifier/IC Enable.
PAGE 7
Data Sheet ADP1872/ADP1873 100 VDD = 5.5V, VIN = 13V (PSM) 95 VDD = 5.5V, VIN = 5.5V VDD = 5.5V, VIN = 16.5V (PSM) 90 85 VDD = 3.6V, VIN = 5.5V VDD = 5.5V, 75 VIN = 5.5V VDD = 5.5V, VIN = 13V (PSM) VDD = 3.6V, VIN = 13V 65 60 VDD = 5.5V, VIN = 16.5V 55 VDD = 3.6V, VIN = 16.5V 50 45 40 30 100 1k 10k 100k LOAD CURRENT (mA) 08297-004 WURTH IND: 744355147, L = 0.47µH, DCR: 0.80mΩ INFINEON FETs: BSC042N03MS G (UPPER/LOWER) TA = 25°C 35 LOAD CURRENT (mA) Figure 4.
PAGE 8
ADP1872/ADP1873 0.8030 VDD = 5.5V, VIN = 5.5V 0.8025 VIN = 5.5V (PSM) 0.8020 0.8015 VDD = 3.6V, VIN = 5.5V VDD = 3.6V, VIN = 3.6V 10k 100k LOAD CURRENT (mA) 0.7960 VIN = 16.5V +125°C +25°C –40°C VIN = 5.5V +125°C +25°C –40°C 0 2000 4000 6000 8000 10,000 12,000 14,000 16,000 LOAD CURRENT (mA) 1.821 OUTPUT VOLTAGE (V) 1.816 1.811 1.806 1.801 1.796 VIN = 5.5V +125°C +25°C –40°C 1.791 1.786 0 1500 3000 4500 VIN = 13V +125°C +25°C –40°C 6000 7500 VIN = 16.
PAGE 9
ADP1872/ADP1873 1.801 1.810 1.800 1.809 1.799 1.808 1.798 1.807 OUTPUT VOLTAGE (V) 1.797 1.796 1.795 1.794 1.793 1.792 1.804 1.803 1.802 1.801 1.789 0 1500 3000 4500 6000 7500 9000 10,500 12,000 13,500 15,000 LOAD CURRENT (mA) 1.798 0 5.040 OUTPUT VOLTAGE (V) 5.038 5.036 5.034 5.032 5.030 5.028 5.026 5.024 VDD = 5.5V, VIN = 13V VDD = 5.5V, VIN = 16.
PAGE 10
ADP1872/ADP1873 325 VDD = 5.5V VDD = 3.6V +125°C +25°C –40°C 340 NO LOAD 315 FREQUENCY (kHz) FREQUENCY (kHz) 295 285 275 265 255 295 280 265 250 235 220 235 205 225 10.8 11.0 11.2 11.4 11.6 11.8 12.0 12.2 12.4 12.6 12.8 13.0 13.2 190 08297-022 245 VIN (V) 0 VDD = 5.5V VDD = 3.6V +125°C +25°C –40°C 2000 4000 6000 8000 10,000 12,000 14,000 16,000 LOAD CURRENT (mA) Figure 25. Frequency vs. Load Current, 300 kHz, VOUT = 0.8 V Figure 22. Switching Frequency vs.
PAGE 11
700 670 640 610 580 550 520 490 460 430 400 370 340 310 280 250 220 190 ADP1872/ADP1873 VIN = 5.5V VIN = 13V VIN = 16.5V 1300 +125°C +25°C –40°C 1150 FREQUENCY (kHz) 1000 925 850 775 700 625 550 2000 4000 6000 8000 10,000 12,000 14,000 16,000 400 0 4000 6000 8000 10,000 12,000 14,000 16,000 LOAD CURRENT (mA) Figure 28. Frequency vs. Load Current, 600 kHz, VOUT = 0.8 V 815 795 775 755 735 715 695 675 655 635 615 595 575 555 535 515 495 2000 08297-031 475 LOAD CURRENT (mA) Figure 31.
PAGE 12
ADP1872/ADP1873 Data Sheet 2.658 680 2.657 630 580 MINIMUM OFF-TIME (ns) 2.656 2.654 2.653 2.652 2.651 530 480 430 380 330 280 2.650 0 20 40 60 80 100 120 TEMPERATURE (°C) 180 –40 08297-034 –20 VDD = 2.7V VDD = 3.6V VDD = 5.5V 95 80 100 120 +125°C +25°C –40°C 580 75 70 65 60 55 530 480 430 380 330 280 50 500 600 700 800 900 1000 FREQUENCY (kHz) 180 2.7 08297-035 400 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V) Figure 35. Maximum Duty Cycle vs. Frequency VDD = 3.
PAGE 13
Data Sheet 1280 1200 1120 ADP1872/ADP1873 VIN = 5.5V VIN = 13V VIN = 16.5V 1MHz 300kHz TA = 25°C OUTPUT VOLTAGE 1 RECTIFIER DROP (mV) 1040 960 880 800 INDUCTOR CURRENT 720 2 640 560 SW NODE 480 400 3 320 240 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V) 640 300kHz 1MHz CH2 5A Ω CH4 5V M400ns T 35.8% A CH2 3.90A Figure 43. Power Saving Mode (PSM) Operational Waveform, 100 mA Figure 40. Internal Boost Rectifier Drop vs.
PAGE 14
ADP1872/ADP1873 Data Sheet OUTPUT VOLTAGE 2 4 OUTPUT VOLTAGE 20A STEP 20A STEP 1 LOW SIDE 1 SW NODE 3 2 SW NODE LOW SIDE 4 B W M2ms T 75.6% A CH1 3.40A 3 CH1 10A Ω CH3 20V Figure 46. Load Transient Step—PSM Enabled, 20 A (See Figure 91 Application Circuit) CH2 5V CH4 200mV B W M2ms T 15.6% A CH1 6.20A 08297-049 CH2 200mV CH4 5V 08297-046 CH1 10A Ω CH3 20V Figure 49.
PAGE 15
Data Sheet ADP1872/ADP1873 OUTPUT VOLTAGE OUTPUT VOLTAGE 1 1 INDUCTOR CURRENT 2 INDUCTOR CURRENT LOW SIDE 2 LOW SIDE 4 4 SW NODE SW NODE 3 M4ms T 49.4% A CH1 920mV CH1 2V BW CH2 5A Ω CH3 10V CH4 5V Figure 52. Output Short-Circuit Behavior Leading to Hiccup Mode 1 M4ms T 41.6% A CH1 720mV 08297-055 CH1 2V BW CH2 5A Ω CH3 10V CH4 5V 08297-052 3 Figure 55.
PAGE 16
ADP1872/ADP1873 Data Sheet TA = 25°C VDD = 5.5V VDD = 3.6V VDD = 2.7V 570 TRANSCONDUCTANCE (µS) LOW SIDE 4 HIGH SIDE SW NODE 3 2 550 530 510 490 470 450 M M40ns T 29.0% A CH2 4.20V 430 –40 08297-058 CH3 5V MATH 2V 40ns CH2 5V CH4 2V 20 40 60 80 100 680 +125°C +25°C –40°C TRANSCONDUCTANCE (µS) 630 4 120 Figure 61. Transconductance (GM) vs. Temperature TA = 25°C 16ns (tf, DRVL) 0 TEMPERATURE (°C) Figure 58.
PAGE 17
Data Sheet ADP1872/ADP1873 ADP1872/ADP1873 BLOCK DIGRAM TO ENABLE ALL BLOCKS PRECISION ENABLE BLOCK COMP/EN tON BIAS BLOCK VDD ADP1872/ ADP1873 VIN FILTER VDD VDD BST REF_ZERO ISS DRVH PFM STATE MACHINE CSS SS_REF DRIVERS ERROR AMP SW 300kΩ SS COMP DRVL 8kΩ FB IREV COMP VREG LOWER COMP CLAMP REF_ZERO PGND PWM 800kΩ CS AMP CS GAIN SET ADC CS GAIN PROGRAMMING GND Figure 64. ADP1872/ADP1873 Block Diagram Rev. B | Page 17 of 40 08297-063 0.
PAGE 18
ADP1872/ADP1873 Data Sheet THEORY OF OPERATION ADP1872/ADP1873 The ADP1872/ADP1873 are versatile current-mode, synchronous step-down controllers that provide superior transient response, optimal stability, and current limit protection by using a constant on-time, pseudo-fixed frequency with a programmable currentsense gain, current-control scheme. In addition, these devices offer optimum performance at low duty cycles by using valley currentmode control architecture.
PAGE 19
Data Sheet ADP1872/ADP1873 PROGRAMMING RESISTOR (RES) DETECT CIRCUIT VALLEY CURRENT-LIMIT SETTING Upon startup, one of the first blocks to become active is the RES detect circuit. This block powers up before soft start begins. It forces a 0.4 V reference value at the DRVL output (see Figure 67) and is programmed to identify four possible resistor values: 47 kΩ, 22 kΩ, open, and 100 kΩ. The architecture of the ADP1872/ADP1873 is based on valley current-mode control.
PAGE 20
ADP1872/ADP1873 Data Sheet Table 6. Valley Current Limit Program1 RON (mΩ) 1.5 2 2.5 3 3.5 4.5 5 5.5 10 15 18 Valley Current Level 22 kΩ Open ACS = 6 V/V ACS = 12 V/V 47 kΩ ACS = 3 V/V 39.0 33.4 26.0 23.4 21.25 11.7 7.75 6.5 23.3 15.5 13.0 31.0 26.0 100 kΩ ACS = 24 V/V 38.9 29.2 23.3 19.5 16.7 13 11.7 10.6 5.83 3.87 3.25 The valley current limit is programmed as outlined in Table 6 and Figure 70.
PAGE 21
Data Sheet ADP1872/ADP1873 SYNCHRONOUS RECTIFIER The ADP1872/ADP1873 employ an internal lower side MOSFET driver to drive the external upper side and lower side MOSFETs. The synchronous rectifier not only improves overall conduction efficiency but also ensures proper charging to the bootstrap capacitor located at the upper side driver input.
PAGE 22
ADP1872/ADP1873 Data Sheet To illustrate this feature more clearly, this section describes one such load transient event—a positive load step—in detail. During load transient events, the high-side driver output pulse width stays relatively consistent from cycle to cycle; however, the off-time (DRVL on-time) dynamically adjusts according to the instantaneous changes in the external conditions mentioned. VIN C I R (TRIMMED) 08297-075 SW INFORMATION Figure 76.
PAGE 23
Data Sheet ADP1872/ADP1873 APPLICATIONS INFORMATION FEEDBACK RESISTOR DIVIDER Table 7. Recommended Inductors The required resistor divider network can be determine for a given VOUT value because the internal band gap reference (VREF) is fixed at 0.6 V. Selecting values for RT and RB determines the minimum output load current of the converter. Therefore, for a given value of RB, the RT value can be determined by L (µH) 0.12 0.22 0.47 0.72 0.9 1.2 1.0 1.4 2.0 0.8 RT = R B × (VOUT − 0.6 V) 0.
PAGE 24
ADP1872/ADP1873 Data Sheet Ceramic capacitors are known to have low ESR. However, the trade-off of using X5R technology is that up to 80% of its capacitance may be lost due to derating because the voltage applied across the capacitor is increased (see Figure 79). Although X7R series capacitors can also be used, the available selection is limited to only up to 22 µF.
PAGE 25
Data Sheet ADP1872/ADP1873 EFFICIENCY CONSIDERATION 800 One of the important criteria to consider in constructing a dc-to-dc converter is efficiency. By definition, efficiency is the ratio of the output power to the input power. For high power applications at load currents up to 20 A, the following are important MOSFET parameters that aid in the selection process: 720    VGS (TH): the MOSFET support voltage applied between the gate and the source.
PAGE 26
ADP1872/ADP1873 Data Sheet Body Diode Conduction Loss INPUT CAPACITOR SELECTION The ADP1872/ADP1873 employ anticross conduction circuitry that prevents the upper side and lower side MOSFETs from conducting current simultaneously. This overlap control is beneficial, avoiding large current flow that may lead to irreparable damage to the external components of the power stage.
PAGE 27
Data Sheet ADP1872/ADP1873 THERMAL CONSIDERATIONS The ADP1872/ADP1873 are used for dc-to-dc, step down, high current applications that have an on-board controller and on-board MOSFET drivers. Because applications may require up to 20 A of load current delivery and be subjected to high ambient temperature surroundings, the selection of external upper side and lower side MOSFETs must be associated with careful thermal consideration to not exceed the maximum allowable junction temperature of 125°C.
PAGE 28
ADP1872/ADP1873 Data Sheet Choose five 270 µF polymer capacitors. The inductor peak current is approximately The rms current through the output capacitor is 15 A + (5 A × 0.5) = 17.5 A Therefore, an appropriate inductor selection is 1.0 µH with DCR = 3.3 mΩ (7443552100) from Table 7 with peak current handling of 20 A. PDCR ( LOSS ) = I RMS = = 2 DCR × I LOAD = 0.003 × (15 A)2 = 675 mW PCOUT = (IRMS)2 × ESR = (1.5 A)2 × 1.4 mΩ = 3.
PAGE 29
Data Sheet ADP1872/ADP1873 Loss Calculations PSW (LOSS) = fSW × RGATE × CTOTAL × ILOAD × VIN × 2 = 300 × 103 × 1.5 Ω × 3.3 × 10−9 × 15 A × 12 × 2 = 534.6 mW Duty cycle = 1.8/12 V = 0.15 RON (N2) = 5.4 mΩ [ ( )] PDR ( LOSS ) = VDR × f SW CupperFETVDR + I BIAS + tBODY(LOSS) = 20 ns (body conduction time) QN1, N2 = 17 nC (total MOSFET gate charge) [VDD × ( f SW ClowerFETVDD + I BIAS )] = (5.12 × (300 × 103 × 3.3 × 10−9 × 5.12 + 0.002)) + (5.5 × (300 × 103 ×3.3 ×10−9 ×5.5 + 0.002)) = 77.
PAGE 30
ADP1872/ADP1873 Data Sheet EXTERNAL COMPONENT RECOMMENDATIONS The configurations listed in Table 8 are with fCROSS = 1/12 × fSW, fZERO = ¼ × fCROSS, RRES = 100 kΩ, RBOT = 15 kΩ, RON = 5.4 mΩ (BSC042N03MS G), VDD = 5 V, and a maximum load current of 14 A. The ADP1873 models listed in Table 8 are the PSM versions of the device. Table 8. External Component Values Marking Code SAP Model ADP1872ARMZ-0.3-R7/ ADP1873ARMZ-0.3-R7 ADP1872ARMZ-0.6-R7/ ADP1873ARMZ-0.6-R7 ADP1872ARMZ-1.0-R7/ ADP1873ARMZ-1.
PAGE 31
Data Sheet ADP1872/ADP1873 Marking Code SAP Model ADP1872 LDV LDV VOUT (V) 5 7 ADP1873 LDL LDL VIN (V) 16.5 16.5 CIN (µF) 3 × 109 3 × 109 COUT (µF) 3 × 476 222 + 476 L1 (µH) 1.0 1.0 RC (kΩ) 34 34 CCOMP (pF) 268 228 CPAR (pF) 27 23 RTOP (kΩ) 110.0 160.0 See the Inductor Selection section (See Table 9). 22 µF Murata 25 V, X7R, 1210 GRM32ER71E226KE15L (3.2 mm × 2.5 mm × 2.5 mm). 3 560 µF Panasonic (SP-series) 2 V, 7 mΩ, 3.7 A EEFUE0D561LR (4.3 mm × 7.3 mm × 4.2 mm).
PAGE 32
ADP1872/ADP1873 Data Sheet LAYOUT CONSIDERATIONS Figure 82 shows the schematic of a typical ADP1872/ADP1873 used for a high power application. Blue traces denote high current pathways. VIN, PGND, and VOUT traces should be wide and possibly replicated, descending down into the multiple layers. Vias should populate, mainly around the positive and negative terminals of the input and output capacitors, alongside the source of Q1/Q2, the drain of Q3/Q4, and the inductor.
PAGE 33
Data Sheet ADP1872/ADP1873 SENSITIVE ANALOG COMPONENTS LOCATED FAR FROM THE NOISY POWER SECTION. SW SEPARATE ANALOG GROUND PLANE FOR THE ANALOG COMPONENTS (THAT IS, COMPENSATION AND FEEDBACK RESISTORS). OUTPUT CAPACITORS ARE MOUNTED ON THE RIGHTMOST AREA OF THE EVB, WRAPPING BACK AROUND TO THE MAIN POWER GROUND PLANE, WHERE IT MEETS WITH THE NEGATIVE TERMINALS OF THE INPUT CAPACITORS BYPASS POWER CAPACITOR (C1) FOR VREG BIAS DECOUPLING AND HIGH FREQUENCY CAPACITOR (C2) AS CLOSE AS POSSIBLE TO THE IC.
PAGE 34
Data Sheet 08297-083 ADP1872/ADP1873 Figure 84. Layer 2 of Evaluation Board Rev.
PAGE 35
Data Sheet ADP1872/ADP1873 TOP RESISTOR FEEDBACK TAP 08297-084 VOUT SENSE TAP LINE EXTENDING BACK TO THE TOP RESISTOR IN THE FEEDBACK DIVIDER NETWORK (SEE FIGURE 82). THIS OVERLAPS WITH PGND SENSE TAP LINE EXTENDING BACK TO THE ANALOG PLANE (SEE FIGURE 86, LAYER 4 FOR PGND TAP). Figure 85. Layer 3 of Evaluation Board Rev.
PAGE 36
ADP1872/ADP1873 Data Sheet BOTTOM RESISTOR TAP TO THE ANALOG GROUND PLANE 08297-085 PGND SENSE TAP FROM NEGATIVE TERMINALS OF OUTPUT BULK CAPACITORS. THIS TRACK PLACEMENT SHOULD BE DIRECTLY BELOW THE VOUT SENSE LINE FROM FIGURE 84. Figure 86. Layer 4 (Bottom Layer) of Evaluation Board Rev.
PAGE 37
Data Sheet ADP1872/ADP1873 IC SECTION (LEFT SIDE OF EVALUATION BOARD) A dedicated plane for the analog ground plane (GND) should be separate from the main power ground plane (PGND). With the shortest path possible, connect the analog ground plane to the GND pin (Pin 4). This plane should only be on the top layer of the evaluation board. To avoid crosstalk interference, there should not be any other voltage or current pathway directly below this plane on Layer 2, Layer 3, or Layer 4.
PAGE 38
ADP1872/ADP1873 Data Sheet TYPICAL APPLICATION CIRCUITS DUAL-INPUT, 300 kHz HIGH CURRENT APPLICATION CIRCUIT LOW VOLTAGE INPUT VDD = 5.0V HIGH VOLTAGE INPUT VIN = 12V JP1 CF 57pF VOUT ADP1872/ ADP1873 1 R1 30kΩ R2 15kΩ C2 0.1µF BST 10 VIN C12 100nF Q1 COMP/EN FB DRVH 8 4 GND PGND 7 5 VDD DRVL 6 C1 1µF 1.0µH Q3 C7 22µF C6 22µF C5 22µF Q2 SW 9 2 3 C4 22µF C3 22µF C20 R6 270µF 2Ω C13 1.5nF Q4 VOUT = 1.
PAGE 39
Data Sheet ADP1872/ADP1873 DUAL-INPUT, 300 kHz HIGH CURRENT APPLICATION CIRCUIT LOW VOLTAGE INPUT VDD = 5V HIGH VOLTAGE INPUT VIN = 13V JP1 CF 80pF VOUT R1 30kΩ R2 15kΩ C2 0.1µF ADP1872/ ADP1873 1 VIN 2 COMP/EN BST 10 3 FB DRVH 8 4 GND PGND 7 5 VDD DRVL 6 C12 100nF C3 22µF Q1 C4 22µF C5 22µF C7 22µF Q2 SW 9 0.8µH Q3 C6 22µF Q4 C1 1µF C20 R6 270µF 2Ω C13 1.5nF VOUT = 1.
PAGE 40
ADP1872/ADP1873 Data Sheet OUTLINE DIMENSIONS 3.10 3.00 2.90 10 3.10 3.00 2.90 5.15 4.90 4.65 6 1 5 PIN 1 IDENTIFIER 0.50 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.30 0.15 6° 0° 0.23 0.13 COMPLIANT TO JEDEC STANDARDS MO-187-BA 0.70 0.55 0.40 091709-A 0.15 0.05 COPLANARITY 0.10 Figure 92. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters ORDERING GUIDE Model1 ADP1872ARMZ-0.3-R7 ADP1872ARMZ-0.6-R7 ADP1872ARMZ-1.0-R7 ADP1872-0.3-EVALZ ADP1872-0.6-EVALZ ADP1872-1.