Datasheet

ADP1853 Data Sheet
Rev. 0 | Page 8 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1 EN Enable Input. Drive EN high to turn on the controller, and drive EN low to turn the controller off. Tie EN to V
IN
for
automatic startup. For a precision UVLO, put an appropriately sized resistor divider from V
IN
to AGND, and tie the
midpoint to this pin.
2 SS Soft Start Input. Connect a capacitor from SS to AGND to set the soft start period. This node is internally pulled up
to VCCO through a 6.5 µA current source.
3 FB Output Voltage Feedback. Connect this pin to an output via a resistor divider. Tie FB to VCCO for slave mode
operation in interleaved dual-phase configuration.
4 COMP Compensation Node. Output of the error amplifier. Connect a resistor-capacitor network from COMP to FB to
compensate the regulation control loop. In interleaved dual-phase configuration, tie this pin to the COMP pin of
the second channel.
5 AGND Analog Ground. Connect to the system AGND plane.
6 SYNC Frequency Synchronization Input. This pin accepts an external clock signal with a frequency close to 1× the
internal oscillator frequency, f
OSC
, set by the FREQ pin. The controller operates in forced PWM when a periodic clock
signal is detected at SYNC or when SYNC is high. The resulting switching frequency is 1× the SYNC frequency.
When SYNC is low or left floating, the controller operates in pulse skip mode.
7 CLKOUT
Internal Clock Output. The CLKOUT is 1× the internal oscillator or input SYNC signal frequency, 180
°
phase-shifted.
This pin can be used to synchronize another
ADP1853 or other controllers.
8 VIN Connect to Main Power Supply. Bypass with a 1 µF or larger ceramic capacitor connected as close to this pin as
possible and AGND.
9 VCCO Output of the Internal Low Dropout Regulator (LDO). The internal circuitry and gate drivers are powered from
VCCO. Bypass VCCO to AGND with a 1 μF or larger ceramic capacitor. The VCCO output remains active even when
EN is low. For operations at V
IN
below 5 V, V
IN
may be jumped to VCCO. Do not use the LDO to power other auxiliary
system loads.
10 PGND Power Ground. Ground for internal driver. Differential current.
11 DL Low-Side Synchronous Rectifier Gate Driver Output. To program the gain of the current sense amplifier in a current
mode or to set voltage mode control, connect a resistor between DL and PGND. This pin is capable of driving
MOSFETs with a total input capacitance up to 20 nF.
12 CS Current Sense Amplifier Input. Differential current is sensed between CS and PGND. Connect this pin to the
current sense resistor or to the SW pin to sense the current. Tie this pin to PGND for voltage mode operation.
13 SW Power Switch Node. Connect this pin to the source of the high-side N-channel MOSFET and the drain of the low-
side N-channel MOSFET.
14 DH High-Side Switch Gate Driver Output. This pin is capable of driving MOSFETs with a total input capacitance up to
20 nF.
15
BST
Boot Strapped Upper Rail of High-Side Internal Driver. Connect a 0.1 µF to a 0.22 µF multilayer ceramic capacitor
(MLCC) between BST and SW. There is an internal boost diode rectifier connected between VCCO and BST.
16 ILIM Current-Limit Sense Comparator Inverting Input. Connect a resistor between ILIM and SW to set the current-
limit offset. For accurate current-limit sensing, connect ILIM to a current sense resistor at the source of the
low-side MOSFET.
14
13
12
1
3
4
DH
15
BST
NOTES
1. CONNECT THE BOTTOM OF THE
EXPOSED PAD TO THE SYSTEM
AGND PLANE.
SW
CS
11
DL
EN
FB
2
SS
COMP
5
AGND
7
CLKOUT
6
SYNC
8
VIN
9
VCCO
10
PGND
19
FREQ
20
TRK
18
RAMP
17
PGOOD
16
ILIM
ADP1853
TOP VIEW
10594-003