Datasheet

ADP1853 Data Sheet
Rev. 0 | Page 24 of 28
As the master voltage rises, the slave voltage rises identically.
Eventually, the slave voltage reaches its regulation voltage,
where the internal reference takes over the regulation while
the TRK input continues to increase, thus removing itself from
influencing the output voltage.
To ensure that the output voltage accuracy is not compromised
by the TRK pin being too close in voltage to the reference volt-
age (V
FB
, typically 0.6 V), make sure that the final value of the
TRK voltage of the slave channel is at least 30 mV above V
FB
.
Ratiometric Tracking
Ratiometric tracking limits the output voltage to a fraction of
the master voltage, as illustrated in Figure 33 and Figure 34. The
final TRK voltage of the slave channel should be set to at least
30 mV below the FB voltage of the master channel. When the
TRK voltage of the slave channel drops to a level that is below
the minimum on time condition, the slave channel operates in
pulse skip mode while keeping the output regulated and tracked
to the master channel. In addition, when TRK or FB drops
below the PGOOD undervoltage threshold, the PGOOD signal
is tripped and becomes active low.
Figure 33. Ratiometric Tracking
Figure 34. Example of a Ratiometric Tracking Circuit
PCB LAYOUT GUIDLINES
The recommended board layout practices for the synchronous
buck controller are described in the AN-1119 Application Note.
MASTER VOLTAGE
SLAVE VOLTAGE
TIME
VOLTAGE (V)
10594-039
ADP1853
FB
SS
TRK
R
BOT
10kΩ
R
TOP
22.6kΩ
0.55V 0.55V
3.3V
V
OUT_MASTER
1.8V
V
OUT_SLAVE
R
TRKB
10kΩ
R
TRKT
49.9kΩ
C
SS
20nF
10594-040