Datasheet

Data Sheet ADP1853
Rev. 0 | Page 23 of 28
Use the larger value of C
I
from Equation 14 or Equation 15.
Because of the finite output current drive of the error amplifier,
C
I
needs to be less than 10 nF. If it is larger than 10 nF, choose a
larger R
TOP
and recalculate R
Z
and C
I
until C
I
is less than 10 nF.
Next, choose the high frequency pole, f
P1
, to be ½ of f
SW
.
SW
P1
ff
2
1
=
(16)
Because C
HF
<< C
I
,
HF
Z
P1
CR
f
π
=
2
1
(17)
Combine Equation 16 and Equation 17, and solve for C
HF
,
Z
SW
HF
Rf
C
π
=
1
(18)
For maximally precise compensation solutions, use the
ADIsimPower design tool.
SWITCHING NOISE AND OVERSHOOT REDUCTION
To reduce voltage ringing and noise, it is recommended to add
an RC snubber between SW and PGND for high current
applications, as illustrated in Figure 30.
In most applications, R
SNUB
is typically 2 Ω to 4 Ω, and C
SNUB
is
typically 1.2 nF to 3 nF.
The size of the RC snubber components must be chosen
correctly to handle the power dissipation. The power dissipated
in R
SNUB
is
SWSNUB
IN
SNUB
fCVP ××=
2
In most applications, a component size of 0805 for R
SNUB
is
sufficient. The RC snubber does not reduce the voltage over-
shoot. A resistor, shown as R
RISE
in Figure 30, at the BST pin
helps to reduce overshoot and is generally between 2 Ω and
4 Ω. Adding a resistor in series, typically between 2 Ω and
4 Ω, with the gate driver also helps to reduce overshoot. If a
gate resistor is added, then R
RISE
is not needed.
Figure 30. Application Circuit with a Snubber
VOLTAGE TRACKING
The ADP1853 includes a tracking feature that tracks a master
voltage. In all tracking configurations, the output can be set as
low as 0.6 V for a given operating condition. The soft start time
setting of the master voltage should be longer than the soft start
of the slave voltage. This forces the rise time of the master
voltage to be imposed on the slave voltage. If the soft start
setting of the slave voltage is longer, the slave comes up more
slowly, and the tracking relationship is not seen at the output.
Two tracking configurations are possible with the ADP1853:
coincident and ratiometric tracking.
Coincident Tracking
The most common application is coincident tracking, used
in core vs. I/O voltage sequencing and similar applications.
Coincident tracking forces the ramp rate of the output voltage
to be the same for the master and slave until the slave output
reaches its regulation. Connect the slave TRK input to a resistor
divider from the master voltage that is the same as the divider
used on the slave FB pin. This forces the slave voltage to be the
same as the master voltage. For coincident tracking, use R
TRKT
=
R
TOP
and R
TRKB
= R
BOT
, as shown in Figure 32.
Figure 31. Coincident Tracking
Figure 32. Example of a Coincident Tracking Circuit
The ratio of the slave output voltage to the master voltage is a
function of the two dividers.








+








+
=
TRKB
TRKT
BOT
TOP
MASTEROUT
SLAVEOUT
R
R
R
R
V
V
1
1
_
_
V
IN
ADP1853
DH
DL
SW
BST
PGND
R
RISE
M1
M2
L
V
OUT
C
SNUB
C
OUT
R
SNUB
10594-036
MASTER VOLTAGE
SLAVE VOLTAGE
TIME
VOLTAGE (V)
10594-037
ADP1853
FB
SS
TRK
R
BOT
10kΩ
R
TOP
20kΩ
1.1V
3.3V
V
OUT_MASTER
1.8V
V
OUT_SLAVE
R
TRKB
10kΩ
R
TRKT
20kΩ
C
SS
20nF
10594-038