Datasheet

Data Sheet ADP1851
Rev. 0 | Page 7 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1 EN Enable Input. Drive EN high to turn the controller on, and drive EN low to turn the controller off. Tie EN to V
IN
for
automatic startup. For a precision UVLO, connect an appropriately sized resistor divider from V
IN
to AGND, and
tie the midpoint to this pin.
2 SS/TRK Soft Start/Tracking Input. Connect a capacitor from SS/TRK to AGND to set the soft start time. This node is
internally pulled up to VCCO through a 6.5 µA current source. Use this pin as the TRK input for tracking an
external voltage during startup.
3 FB Output Voltage Feedback Input. Connect this pin to an output via a resistor divider.
4 COMP Compensation Node. Output of the error amplifier. Connect a resistor/capacitor (RC) network from COMP to FB
to compensate the regulation control loop.
5
SYNC
Frequency Synchronization Input. This pin accepts an external clock signal with a frequency close to 1× the
internal oscillator frequency, f
OSC
, set by the FREQ pin. The controller operates in forced PWM mode when a
periodic clock signal is detected at SYNC or when SYNC is high (connected to VCCO). The resulting switching
frequency is 1× the SYNC frequency. When SYNC is low or left floating, the controller operates in pulse skip
mode.
6 VIN Input Voltage. Connect to main power supply. Bypass with a 1 µF or larger ceramic capacitor connected as close
as possible to this pin and AGND.
7 VCCO Output of the Internal Low Dropout (LDO) Regulator. The internal circuitry and gate drivers are powered from
VCCO. Bypass VCCO to AGND with a 1 μF or larger ceramic capacitor. The VCCO output remains active even
when EN is low. For operations at V
IN
below 5.5 V, VIN can be connected to VCCO. Do not use the LDO to power
other auxiliary system loads.
8 PGND Power Ground. Ground for internal driver. Differential current is sensed between SW and PGND.
9 DL Low-Side Synchronous Rectifier Gate Driver Output. To program the gain of the current sense amplifier in a
current mode or to set voltage mode control, connect a resistor between DL and PGND. This pin is capable of
driving MOSFETs with a total input capacitance up to 20 nF.
10 SW Power Switch Node/Current Sense Amplifier Input. Connect this pin to the source of the high-side N-channel
MOSFET and the drain of the low-side N-channel MOSFET. Differential current is sensed between SW and PGND.
11
DH
High-Side Switch Gate Driver Output. This pin is capable of driving MOSFETs with a total input capacitance up
to 20 nF.
12 BST Bootstrapped Upper Rail of High-Side Internal Driver. Connect a multilayer ceramic capacitor (MLCC) with a
value from 0.1 µF to 0.22 µF between BST and SW. An internal boost diode rectifier is connected between VCCO
and BST.
13
ILIM
Current-Limit Sense Comparator Inverting Input. Connect a resistor between ILIM and SW to set the current-
limit offset. For accurate current-limit sensing, connect ILIM to a current sense resistor at the source of the
low-side MOSFET.
14 PGOOD Power Good. PGOOD is the open-drain power-good indicator logic output with an internal 12.5 kΩ resistor
connected between PGOOD and VCCO.
15 RAMP Programmable Current Setting for Slope Compensation. Connect a resistor from RAMP to V
IN
. The voltage at
RAMP is 0.2 V during operation. This pin is high impedance when the controller is disabled.
NOTES
1. THE EXPOSED PAD IS THE AGND
POWER INPUT OF THE IC; CONNECT
IT TO THE SYSTEM AGND PLANE.
12
11
10
1
3
4
BST
DH
SW
9
DL
EN
FB
2
SS/TRK
COMP
6
VIN
5
SYNC
7
VCCO
8
PGND
16 FREQ
15 RAMP
14
PGOOD
13
ILIM
TOP
VIEW
ADP1851
10595-003