Datasheet

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Wide Range Input, Synchronous,

Step-Down DC-to-DC Controller

Data Sheet

ADP1851

Rev. 0

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FEATURES

Input voltage range: 2.75 V to 20 V

Output voltage range: 0.6 V to 90% V

Maximum output current of more than 25 A

Current mode architecture

Configurable to voltage mode

±1% output voltage accuracy over temperature

Voltage tracking

Programmable frequency: 200 kHz to 1.5 MHz

Synchronization input

Power saving mode at light load

Precision enable input

Power good with internal pull-up resistor

Adjustable soft start

Programmable current sense gain

Integrated bootstrap diode

Starts into a precharged load

Externally adjustable slope compensation

Suitable for any output capacitor

Overvoltage and overcurrent-limit protection

Thermal overload protection

Input undervoltage lockout (UVLO)

Available in 16-lead, 4 mm × 4 mm LFCSP

Supported by ADIsimPower design tool

APPLICATIONS

Intermediate bus and POL systems requiring sequencing and

tracking, including

Telecom base station and networking

Industrial and instrumentation

Medical and healthcare

GENERAL DESCRIPTION

The ADP1851 is a wide range input, dc-to-dc, synchronous

buck controller capable of running from commonly used 3.3 V

to 12 V (up to 20 V) voltage inputs. The device nominally

operates in current mode with valley current sensing providing

the fastest step response for digital loads. It can also be config-

ured as a voltage mode controller with low noise and crosstalk

for sensitive loads.

The ADP1851 is ideal in system applications requiring multiple

output voltages. The ADP1851 includes a synchronization

feature to eliminate beat frequencies between switching devices.

It also provides accurate tracking capability between supplies

and includes precision enable and power-good functions for

simple, robust sequencing.

TYPICAL OPERATION CIRCUIT

Figure 1.

The ADP1851 provides a high speed, high peak current gate

driving capability to enable energy efficient power conversion.

The device can be configured to operate in power saving mode

by skipping pulses, reducing switching losses, and improving

efficiency at light load and standby conditions.

The accurate current limit allows design within a narrower

range of tolerances and can reduce overall converter size and

cost. The ADP1851 can regulate down to 0.6 V output using a

high accuracy reference with ±1% tolerance over the

temperature range of −40°C to +125°C.

With its wide range input voltage, the ADP1851 provides the

designer with maximum flexibility for use in a variety of system

configurations; loop compensation, soft start, frequency setting,

power saving mode, current limit, and current sense gain can all

be programmed using external components. In addition, the

external RAMP resistor allows the selection of optimal slope

and V

feedforward in both current and voltage modes for

excellent line rejection. The linear regulator and the bootstrap

diode for the high-side driver are internal.

Protection features include undervoltage lockout, overvoltage,

overcurrent/short circuit, and overtemperature.

VIN

PGND

OUT

BST

CSG

RAMP

PGOOD

SYNC

SS/TRK

ILIM

AGND (EP)

COMP

FREQ

VCCO

ADP1851

HIGH

LOW

10595-001

Summary of content (24 pages)

PAGE 1
Wide Range Input, Synchronous, Step-Down DC-to-DC Controller ADP1851 Data Sheet FEATURES APPLICATIONS Intermediate bus and POL systems requiring sequencing and tracking, including Telecom base station and networking Industrial and instrumentation Medical and healthcare GENERAL DESCRIPTION The ADP1851 is a wide range input, dc-to-dc, synchronous buck controller capable of running from commonly used 3.3 V to 12 V (up to 20 V) voltage inputs.
PAGE 2
ADP1851 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Enable/Disable Control ............................................................. 14 Applications ....................................................................................... 1 Thermal Overload Protection .................................................. 14 General Description ......................................................................
PAGE 3
Data Sheet ADP1851 SIMPLIFIED BLOCK DIAGRAM VCCO VIN THERMAL SHUTDOWN LDO AGND (EPAD) OV 0.6V UV REF VCCO UVLO OV 0.63V LOGIC UV LOGIC EN_SW 12.5kΩ EN PGOOD OV_TH FB SYNC 1MΩ UV_TH PH OSCILLATOR FREQ COMP VCCO – SS/TRK + + ERROR AMPLIFIER VREF = 0.6V – VCCO 6.5µA LOGIC FAULT 3kΩ 0.
PAGE 4
ADP1851 Data Sheet SPECIFICATIONS All limits at temperature extremes, TJMIN and TJMAX, are guaranteed via correlation using standard statistical quality control (SQC). VIN = 12 V. The specifications are valid for TJ = −40°C to +125°C, unless otherwise specified. Typical values are at TA = 25°C. Table 1.
PAGE 5
Data Sheet Parameter SYNC Logic Input Low SYNC Logic Input High SYNC Input Pull-Down Resistance GATE DRIVERS DH Rise Time DH Fall Time DL Rise Time DL Fall Time DH to DL Dead Time DH or DL Driver RON, Sourcing Current1 DH or DL Driver RON, Tempco DH or DL Driver RON, Sinking Current1 ADP1851 Symbol 1 Unit V V MΩ INTEGRATED RECTIFIER (BOOST DIODE) RESISTANCE ZERO CURRENT CROSS OFFSET (SW TO PGND)1 1 2 Min Typ Max 1.
PAGE 6
ADP1851 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 2. Parameter VIN, EN, RAMP FB, COMP, SS/TRK, FREQ, SYNC, VCCO, PGOOD ILIM, SW to PGND BST, DH to PGND DL to PGND BST to SW BST to PGND, 20 ns Transients SW to PGND, 20 ns Transients DL, SW, ILIM to PGND, 20 ns Negative Transients PGND to AGND PGND to AGND, 20 ns Transients θJA (Natural Convection)1, 2 Operating Junction Temperature Range3 Storage Temperature Range Maximum Soldering Lead Temperature Rating 21 V −0.3 V to +6 V −0.3 V to +21 V −0.
PAGE 7
Data Sheet ADP1851 13 ILIM 14 PGOOD 16 FREQ 15 RAMP PIN CONFIGURATION AND FUNCTION DESCRIPTIONS EN 1 12 BST ADP1851 11 DH TOP VIEW 10 SW FB 3 9 VCCO 7 DL PGND 8 VIN 6 SYNC 5 COMP 4 NOTES 1. THE EXPOSED PAD IS THE AGND POWER INPUT OF THE IC; CONNECT IT TO THE SYSTEM AGND PLANE. 10595-003 SS/TRK 2 Figure 3. Pin Configuration Table 3. Pin Function Descriptions Pin No.
PAGE 8
ADP1851 Pin No. 16 Mnemonic FREQ EPAD (AGND) Data Sheet Description Internal Oscillator Frequency, fOSC. Sets the desired operating frequency between 200 kHz and 1.5 MHz with one resistor between FREQ and AGND. Connect FREQ to AGND for a preprogrammed 300 kHz, or tie FREQ to VCCO for 600 kHz operating frequency. Exposed Pad, Analog Ground. The exposed pad is the AGND power input of the IC. Connect the exposed pad to the system AGND plane. Rev.
PAGE 9
Data Sheet ADP1851 TYPICAL PERFORMANCE CHARACTERISTICS 90 90 80 80 70 70 EFFICIENCY (%) 60 50 40 60 50 40 30 30 20 20 10 10 1 10 100 LOAD (A) 0 0.1 10595-004 0 0.1 PULSE SKIP FORCED PWM 1 10 100 LOAD (A) Figure 4. Efficiency Plot 12 VIN to 1.8 VOUT, 600 kHz (see Figure 34 for Circuit) Figure 7. Efficiency Plot 12 VIN to 3.3 VOUT, 300 kHz (see Figure 35 for Circuit) LOAD CURRENT LOAD CURRENT 4 4 VOUT_AC VOUT_AC M 100µs 50MS/s 20ns/pt B W B W A CH4 13.
PAGE 10
ADP1851 Data Sheet EN SYNC 1 1 SW 3 DH 3 VOUT DL M 1.0µs 250MS/s A CH1 4ns/pt B W CH3 10V BW CH4 5V B W 3.1V 10595-010 CH1 5V Figure 10. Synchronization, fSYNC = 600 kHz B CH3 10V B W CH2 500mV W B W M 2ms 250kS/s 4µs/pt A CH1 580mV Figure 13. Soft Start with Precharged Output, 1.
PAGE 11
Data Sheet ADP1851 THEORY OF OPERATION CONTROL ARCHITECTURE The ADP1851 is based on a fixed frequency, emulated peak current mode, PWM control architecture. The inductor current is sensed by the voltage drop measured across the external lowside MOSFET, RDSON, or across the sense resistor placed in series between the low-side MOSFET source and the power ground. The current is sensed during the off period of the switching cycle and is conditioned with the internal current sense amplifier.
PAGE 12
ADP1851 Data Sheet SYNCHRONIZATION SW The switching frequency of the ADP1851 can be synchronized to an external clock signal by connecting it to the SYNC pin. The internal oscillator frequency, programmed by the resistor at the FREQ pin, must be set close to the external clock frequency; therefore, the external clock frequency can vary between 0.85× and 1.3× the internal clock set. The resulting switching frequency is 1× the external SYNC frequency. When synchronized, the ADP1851 operates in PWM mode.
PAGE 13
Data Sheet ADP1851 SYNCHRONOUS RECTIFIER AND DEAD TIME VIN = 2.75V TO 5.5V When the bias input voltage at the VIN pin is less than the undervoltage lockout (UVLO) threshold of 2.65 V typical, the switch drivers stay inactive. If EN is high, the controller starts switching and the VIN pin voltage exceeds the UVLO threshold. INTERNAL LINEAR REGULATOR The internal linear regulator is a low dropout (LDO) VCCO. VCCO powers up the internal control circuitry and provides power for the gate drivers.
PAGE 14
ADP1851 Data Sheet SHORT-CIRCUIT AND CURRENT-LIMIT PROTECTION ENABLE/DISABLE CONTROL When the output is shorted or the output current exceeds the current limit set by the current-limit setting resistor (between ILIM and SW) for eight consecutive cycles, the ADP1851 shuts off both the high-side and low-side drivers and restarts the soft start sequence every 10 ms, which is known as hiccup mode. The SS node discharges to zero through an internal 3 kΩ resistor during an overcurrent or short-circuit event.
PAGE 15
Data Sheet ADP1851 APPLICATIONS INFORMATION ADIsimPower DESIGN TOOL SETTING THE CURRENT LIMIT The ADP1851 is supported by the ADIsimPower™ design tool set. ADIsimPower is a collection of tools that produce complete power designs optimized for a specific design goal. The tools allow the user to generate a full schematic and bill of materials and to calculate performance in minutes.
PAGE 16
ADP1851 Data Sheet VIN PIN FILTER OUTPUT CAPACITOR SELECTION It is recommended that a low-pass filter be connected to the VIN pin. Connecting a resistor, between 2 Ω and 10 Ω, in series with VIN and a 1 µF ceramic capacitor between VIN and AGND creates a low-pass filter that effectively filters out any unwanted glitches caused by the switching regulator. Keep in mind that the input current may be larger than 100 mA when driving large MOSFETs.
PAGE 17
Data Sheet ADP1851 MOSFET SELECTION If QGSW is not given in the data sheet, it can be approximated by The choice of MOSFET directly affects the dc-to-dc converter performance. A MOSFET with low on resistance reduces I2R losses, and low gate charge reduces transition losses. The MOSFET should have low thermal resistance to ensure that the power dissipated in the MOSFET does not result in excessive MOSFET die temperature.
PAGE 18
ADP1851 Data Sheet There is also additional power loss during the time, known as dead time, between the turn-off of the high-side switch and the turn-on of the low-side switch, when the body diode of the lowside MOSFET conducts the output current. The power loss in the body diode is given by Type III Compensation Note that the MOSFET on resistance, RDSON, increases with increasing temperature, with a typical temperature coefficient of 0.4%/°C.
PAGE 19
Data Sheet ADP1851 Because CHF << CI, calculate CHF as follows: 1 πf SW R Z (11) Next, calculate the feedforward capacitor, CFF, assuming RFF << RTOP. R FF = 1 Figure 27 illustrates the connection of the slope compensation resistor, RRAMP, and the current sense gain resistor, RCSG. (12) πC FF f SW RRAMP RAMP Check that the calculated component values are reasonable. For example, capacitors smaller than about 10 pF should be avoided.
PAGE 20
ADP1851 Data Sheet Use the larger value of CI from Equation 16 or Equation 17. Because of the finite output current drive of the error amplifier, CI must be less than 10 nF. If it is larger than 10 nF, choose a larger RTOP and recalculate RZ and CI until CI is less than 10 nF. ACS is the current sense amplifier gain. VCOMPMAX is the maximum voltage at the COMP pin. tON is the high-side driver (DH) on time. Replace RDSON with the resistance value of the current sense element, RCS, if it is used.
PAGE 21
Data Sheet ADP1851 The ADP1851 includes a tracking feature that tracks a master voltage. In all tracking configurations, the output can be set as low as 0.6 V for a given operating condition. Two tracking configurations are possible with the ADP1851: coincident and ratiometric tracking. Coincident Tracking The most common application is coincident tracking, used in core vs. I/O voltage sequencing and similar applications.
PAGE 22
ADP1851 Data Sheet TYPICAL OPERATING CIRCUITS VIN = 9V TO 15V TO VCCO 140kΩ 16 EN PGOOD CIN 13 12 2 11 ADP1851 3 COMP 10 EP 4 75pF 2.49kΩ 9 6 7 VIN SYNC 5 VCCO 620pF 14 1 SS/TRK FB 21kΩ 15 BST 0.1µF DH 2Ω M1 L SW DL COUT M2 VOUT 1.8V 25A 8 PGND 0.1µF 1.15kΩ ILIM RAMP FREQ 4.99kΩ 1µF 2Ω TO VIN fSW = 600kHz CIN: OS-CON 150µF/20V, 20SEP150M, SANYO + 2× CAP CER 10µF 25V X7R 1210, MURATA GRM32DR71E106KA12 L: 0.
PAGE 23
Data Sheet ADP1851 OUTLINE DIMENSIONS PIN 1 INDICATOR 0.35 0.30 0.25 0.65 BSC PIN 1 INDICATOR 16 13 1 12 EXPOSED PAD 2.60 2.50 SQ 2.40 9 TOP VIEW 0.80 0.75 0.70 0.50 0.40 0.30 4 8 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 5 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WGGC. 042709-A 4.10 4.00 SQ 3.90 Figure 36.