Datasheet

ADP1850 Data Sheet
Rev. A | Page 6 of 32
SIMPLIFIED BLOCK DIAGRAM
DUPLICATE FOR
CHANNEL 2
BST1
PGND1
+
–
+
–
+
–
+
–
+
–
+
–
FB1
0.6V
OV
UV
PGOOD1
CURRENT SENSE
AMPLIFIER
DH1
DL1
ILIM1
SW1
V
R
E
F
=
0
.
6
V
6.5µA
+
+
–
ERROR
AMPLIFIER
FB1
COMP1
SS1
PWM
COMPARATOR
SLOPE COMP AND
RAMP GENERATOR
CURRENT
LIMIT
CONTROL
VDL
RAMP1
50µA
5V
G
m
OV1
+
TRK1
CS GAIN
DRIVER LOGIC
CONTROL AND
STATE
MACHINE
OVER_LIM1
PULSE SKIP
OVER_LIM1
LDO
LOGIC
EN1
EN2
V
IN
UVLO
OSCILLATOR
FREQ
SYNC
PH1
PH2
REF
V
CCO
OV
UV
0.6V
THERMAL
SHUTDOWN
AGND
0.6V
+
–
+
–
VCCO
VDL
FAULT
OV1
LOGIC
OVER_LIM1
OV1
EN1
EN1_SW
LOGIC
UV1
1kΩ
0.9V
DCM
ZERO CROSS
DETECT
12kΩ
A
V
= 3, 6, 12, 24
VCCO
SYNC
EN1_SW
EN2_SW
1MΩ
–
+
0
9440-003
Figure 2.