Datasheet

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Wide Range Input, Dual/Two-Phase, DC-to-DC

Synchronous Buck Controller

Data Sheet

ADP1850

Rev. A

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FEATURES

Wide range input: 2.75 V to 20 V

Power stage input voltage: 1 V to 20 V

Output voltage range: 0.6 V up to 90% V

Output current to more than 25 A per channel

Accurate current sharing between channels (interleaved)

Programmable frequency: 200 kHz to 1.5 MHz

180° phase shift between channels for reduced input

capacitance

±0.85% reference voltage accuracy from −40°C to +85°C

Integrated boost diodes

Power saving mode (PSM) at light loads

Accurate power good with internal pull-up resistor

Accurate voltage tracking capability

Independent channel precision enable

Overvoltage and overcurrent limit protection

Externally programmable soft start, slope compensation and

current sense gain

Synchronization input

Thermal overload protection

Input undervoltage lockout (UVLO)

Available in 32-lead 5 mm × 5 mm LFCSP

APPLICATIONS

High current single and dual output intermediate bus and

point of load converters requiring sequencing and

tracking capability, including converters for:

Point-of-load power supplies

Telecom base station and networking

Consumer

Industrial and instrumentation

Healthcare and medical

GENERAL DESCRIPTION

The ADP1850 is a configurable dual output or two-phase, single

output dc-to-dc synchronous buck controller capable of running

from commonly used 3.3 V to 12 V (up to 20 V) voltage inputs.

The device operates in current mode for improved transient

response and uses valley current sensing for enhanced noise

immunity.

The architecture enables accurate current sharing between

interleaved phases for high current outputs.

The ADP1850 is ideal in system applications requiring multiple

output voltages: the ADP1850 includes a synchronization fea-

ture to eliminate beat frequencies between switching devices;

provides accurate tracking capability between supplies and

includes precision enable for simple, robust sequencing.

TYPICAL OPERATION CIRCUIT

RAMP1

VIN

DH1

BST1

SW1

ILIM1

FB1

DL1

PGND1

RAMP2

DH2

BST2

SW2

ILIM2

FB2

DL2

PGND2

EN1

EN2

VDL

VCCO

TRK1

TRK2

SYNC

FREQ

COMP1

COMP2

SS1

SS2

AGND

CSG1

R11

R12

R21

R22

CSG2

OUT1

OUT2

RAMP2

PGOOD1

PGOOD2

ADP1850

09440-001

Figure 1. Single Phase Circuit

The ADP1850 provides high speed, high peak current drive

capability with dead-time optimization to enable energy

efficient power conversion. For low load operation, the device

can be configured to operate in power saving mode (PSM) by

skipping pulses and reducing switching losses to improve the

energy efficiency at light load and standby conditions.

The accurate current limit (±6%) allows the power architect to

design within a narrower range of tolerances and can reduce

overall converter size and cost.

The ADP1850 provides a configurable architecture capable

of wide range input operation to provide the designer with

maximum re-use opportunities and improved time to market.

Additional flexibility is provided by external programmability

of loop compensation, soft start, frequency setting, power

saving mode, current limit and current sense gain can all be

programmed using external components.

The ADP1850 includes a high level of integration in a small size

package. The start-up linear regulator and the boot-strap diode

for the high side drive are included. Protection features include:

undervoltage lock-out, overvoltage, overcurrent/short-circuit

and over temperature. The ADP1850 is available in a compact

32-lead LFCSP 5 mm × 5 mm thermally enhanced package.

Summary of content (32 pages)

PAGE 1
Wide Range Input, Dual/Two-Phase, DC-to-DC Synchronous Buck Controller ADP1850 Data Sheet Wide range input: 2.75 V to 20 V Power stage input voltage: 1 V to 20 V Output voltage range: 0.6 V up to 90% VIN Output current to more than 25 A per channel Accurate current sharing between channels (interleaved) Programmable frequency: 200 kHz to 1.5 MHz 180° phase shift between channels for reduced input capacitance ±0.
PAGE 2
ADP1850 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Accurate Current-Limit Sensing .............................................. 17 Applications ....................................................................................... 1 Setting the Slope Compensation .............................................. 17 General Description .........................................................................
PAGE 3
Data Sheet ADP1850 SPECIFICATIONS All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). VIN = 12 V. The specifications are valid for TJ = −40°C to +125°C, unless otherwise specified. Typical values are at TA = 25°C. Table 1.
PAGE 4
ADP1850 Data Sheet Parameter GATE DRIVERS DHx Rise Time DHx Fall Time DLx Rise Time DLx Fall Time DHx to DLx Dead Time DHx or DLx Driver RON, Sourcing Current1 Symbol Conditions RON_SOURCE CDH = 3 nF, VBST − VSW = 5 V CDH = 3 nF, VBST − VSW = 5 V CDL = 3 nF CDL = 3 nF External 3 nF is connected to DHx and DLx Sourcing 2 A with a 100 ns pulse 16 14 16 14 25 2 ns ns ns ns ns Ω DHx or DLx Driver RON, Tempco DHx or DLx Driver RON, Sinking Current1 TCRON RON_SINK Sourcing 1 A with a 100 ns pulse, VIN
PAGE 5
Data Sheet ADP1850 ABSOLUTE MAXIMUM RATINGS Table 2.
PAGE 6
ADP1850 Data Sheet SIMPLIFIED BLOCK DIAGRAM VIN THERMAL SHUTDOWN VCCO AGND UVLO 0.6V EN1_SW EN2_SW LOGIC + – EN1 OV 0.6V UV REF LDO + EN2 VCCO – OV1 LOGIC SYNC UV1 PH1 1MΩ FREQ COMP1 FB1 TRK1 SS1 FB1 0.6V – + + Gm + + – UV VDL BST1 SYNC EN1_SW VREF = 0.6V FAULT 1kΩ LOGIC 5V 0.9V OV1 EN1 OVER_LIM1 DH1 DRIVER LOGIC CONTROL AND STATE MACHINE OVER_LIM1 – 6.
PAGE 7
Data Sheet ADP1850 32 31 30 29 28 27 26 25 TRK1 FB1 COMP1 RAMP1 SS1 PGOOD1 ILIM1 BST1 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 ADP1850 TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 SW1 DH1 PGND1 DL1 DL2 PGND2 DH2 SW2 NOTES 1. CONNECT THE BOTTOM EXPOSED PAD OF THE LFCSP PACKAGE TO SYSTEM AGND PLANE. 09440-004 TRK2 FB2 COMP2 RAMP2 SS2 PGOOD2 ILIM2 BST2 9 10 11 12 13 14 15 16 EN1 SYNC VIN VCCO VDL AGND FREQ EN2 Figure 3. Pin Configuration Table 3.
PAGE 8
ADP1850 Pin No. 15 Mnemonic ILIM2 16 BST2 17 SW2 18 DH2 19 PGND2 20 DL2 21 DL1 22 PGND1 23 DH1 24 SW1 25 BST1 26 ILIM1 27 PGOOD1 28 SS1 29 RAMP1 30 COMP1 31 32 33 (EPAD) FB1 TRK1 Exposed Pad (EPAD) Data Sheet Description Current Limit Sense Comparator Inverting Input for Channel 2. Connect a resistor between ILIM2 and SW2 to set the current limit offset. For accurate current limit sensing, connect ILIM2 to a current sense resistor at the source of the low-side MOSFET.
PAGE 9
Data Sheet ADP1850 TYPICAL PERFORMANCE CHARACTERISTICS 100 5.10 90 5.05 VO = 3.3V, PSM 80 100mA LOAD ON LDO 70 4.95 60 VCCO (V) VO = 3.3V, PWM 50 VO = 1.8V, PSM 40 4.90 4.85 4.80 30 VO = 1.8V, PWM 20 4.75 4.70 10 VIN = 12V, 600kHz 0.1 1 10 100 LOAD (A) 4.65 09440-005 0 0.01 5 7 9 11 13 15 17 5 6 VIN (V) Figure 4. Efficiency Plot of Figure 44 09440-008 EFFICIENCY (%) NO LOAD ON LDO 5.00 Figure 7. LDO Line Regulation 100 6 90 5 80 VO = 5V, PSM 4 60 VO = 1.
PAGE 10
ADP1850 Data Sheet SW1 OUTPUT RESPONSE 1 1 PGOOD1 VCCO (CH3) 8A TO 13A STEP LOAD 2 VOUT, PRELOADED (CH4) 3 VIN = 12V VOUT = 3.3V B W M200µs A CH4 11.5A CH4 5A Ω 4 CH1 10V CH2 2V CH4 2V Ω CH3 2V Figure 10. Step Load Transient of Figure 44 M10ms A CH2 09440-014 CH1 20mV 09440-011 4 3.76V Figure 13. Thermal Shutdown Waveform 0.5 REFERENCED AT VIN = 2.75V 0 DH1 CHANGE IN fSW (%) 1 DL1 2 VOUT1 3 IL1 –0.5 600kHz –1.0 300kHz –1.5 4 VIN = 12V VOUT = 1.
PAGE 11
Data Sheet ADP1850 45 350 TA = 25°C OUTPUT IS LOADED HS FET = BSC080N03LS LS FET = BSC030N03LS 43 300 41 DH MINIMUM OFF TIME 39 DEAD TIME (ns) 200 150 37 35 33 31 DH MINIMUM ON TIME 29 27 5.0 7.5 10.0 12.5 15.0 17.5 20.0 VIN (V) 25 09440-017 50 2.5 DEAD TIME BETWEEN SW FALLING EDGE AND DL RISING EDGE, INCLUDING DIODE RECOVERY TIME 0 5 Figure 16. Typical DH Minimum On Time and Off Time 600 20 VIN = 2.
PAGE 12
ADP1850 Data Sheet THEORY OF OPERATION The ADP1850 is a current mode, dual-channel, step-down switching controller with integrated MOSFET drivers for external N-channel synchronous power MOSFETs. The two outputs are phase shifted 180°. This reduces the input RMS ripple current, thus minimizing required input capacitance. In addition, the two outputs can be combined for dual-phase PWM operation that can deliver more than 50 A output current and the two channels are optimized for current sharing.
PAGE 13
Data Sheet ADP1850 MODES OF OPERATION The SYNC pin is a multifunctional pin. PWM mode is enabled when SYNC is connected to VCCO or a high logic. With SYNC connected to ground or left floating, the pulse skip mode is enabled. Switching SYNC from low to high or high to low on the fly causes the controller to transition from forced PWM to pulse skip mode or pulse skip mode to forced PWM, respectively, in two clock cycles.
PAGE 14
ADP1850 Data Sheet VIN = 2.75V TO 5.5V SYNCHRONOUS RECTIFIER AND DEAD TIME When the bias input voltage, VIN, is less than the undervoltage lockout (UVLO) threshold, the switch drivers stay inactive. When VIN exceeds the UVLO threshold, the switchers start switching. INTERNAL LINEAR REGULATOR The internal linear regulator is low dropout (LDO) meaning it can regulate its output voltage, VCCO. VCCO powers up the internal control circuitry and provides power for the gate drivers.
PAGE 15
Data Sheet ADP1850 SHUTDOWN CONTROL When the output is shorted or the output current exceeds the current limit set by the current limit setting resistor (between ILIMx and SWx) for eight consecutive cycles, the ADP1850 shuts off both the high-side and low-side drivers and restarts the soft start sequence every 10 ms, which is known as hiccup mode. The SS node discharges to zero through an internal 1 kΩ resistor during an overcurrent or short-circuit event.
PAGE 16
ADP1850 Data Sheet APPLICATIONS INFORMATION SETTING THE OUTPUT VOLTAGE The output voltage is set using a resistive voltage divider from the output to FB. The voltage divider divides down the output voltage to the 0.6 V FB regulation voltage to set the regulation output voltage. The output voltage can be set to as low as 0.6 V and as high as 90% of the power input voltage. The maximum input bias current into FB is 100 nA. For a 0.
PAGE 17
Data Sheet ADP1850 VIN ACCURATE CURRENT-LIMIT SENSING RRAMP RDSON of the MOSFET can vary by more than 50% over the temperature range. Accurate current limit sensing is achieved by adding a current sense resistor from the source of the lowside MOSFET to PGNDx. Make sure that the power rating of the current sense resistor is adequate for the application. Apply the previous equation and calculate RILIM by replacing RDSON_MAX with RSENSE.
PAGE 18
ADP1850 Data Sheet INPUT CAPACITOR SELECTION INPUT FILTER The input current to a buck converter is a pulse waveform. It is zero when the high-side switch is off and approximately equal to the load current when it is on. The input capacitor carries the input ripple current, allowing the input power source to supply only the direct current. The input capacitor needs sufficient ripple current rating to handle the input ripple, as well as an ESR that is low enough to mitigate input voltage ripple.
PAGE 19
Data Sheet ADP1850 OUTPUT CAPACITOR SELECTION Choose the output bulk capacitor to set the desired output voltage ripple. The impedance of the output capacitor at the switching frequency multiplied by the ripple current gives the output voltage ripple. The impedance is made up of the capacitive impedance plus the nonideal parasitic characteristics, the equivalent series resistance (ESR), and the equivalent series inductance (ESL).
PAGE 20
ADP1850 Data Sheet The high-side MOSFET transition loss is approximated by the equation PT ≅ The total power dissipation of the high-side MOSFET is the sum of conduction and transition losses: VIN × I LOAD × (t R + t F ) × f SW PHS ≅ PC + PT 2 The synchronous rectifier, or low-side MOSFET, carries the inductor current when the high-side MOSFET is off. The lowside MOSFET transition loss is small and can be neglected in the calculation.
PAGE 21
Data Sheet ADP1850 LOOP COMPENSATION (SINGLE PHASE OPERATION) As with most current mode step-down controller, a transconductance error amplifier is used to stabilize the external voltage loop. Compensating the ADP1850 is fairly easy; an RC compensator is needed between COMPx and AGND. Figure 33 shows the configuration of the compensation components: RCOMP, CCOMP, and CC2. Because CC2 is very small compared to CCOMP, to simplify calculation, CC2 is ignored for the stability compensation analysis.
PAGE 22
ADP1850 Data Sheet CONFIGURATION AND LOOP COMPENSATION (DUAL-PHASE OPERATION) SWITCHING NOISE AND OVERSHOOT REDUCTION In dual-phase operation, the two outputs of the switching regulators are shorted together and can source more than 50 A of output current depending on the selection of the power components. Internal parameters in the ADP1850 are optimized and trimmed in the factory to minimize the mismatch in output currents between the two channels.
PAGE 23
Data Sheet ADP1850 VOLTAGE TRACKING Two tracking configurations are possible with the ADP1850: coincident and ratiometric trackings. Coincident Tracking The most common application is coincident tracking, used in core vs. I/O voltage sequencing and similar applications. Coincident tracking forces the slave output voltage’s ramp rate to be the same as the master’s until the slave output reaches its regulation.
PAGE 24
ADP1850 Data Sheet Another ratiometric tracking configuration is having the slave channel rise more quickly than the master channel, as shown in Figure 40 and Figure 41. The tracking circuits in Figure 39 and Figure 41 are virtually identical with the exception that RTRKB > RTRKT as shown in Figure 41.
PAGE 25
Data Sheet ADP1850 PCB LAYOUT GUIDELINES VIN In any switching converter, there are some circuit paths that carry high dI/dt, which can create spikes and noise. Some circuit paths are sensitive to noise, while other circuits carry high dc current and can produce significant IR voltage drops. The key to proper PCB layout of a switching converter is to identify these critical paths and arrange the components and the copper area accordingly.
PAGE 26
ADP1850 Data Sheet The switch node is the noisiest place in the switcher circuit with large ac and dc voltages and currents. This node should be wide to minimize resistive voltage drop. To minimize capacitively coupled noise, the total area should be small. Place the FETs and inductor close together on a small copper plane to minimize series resistance and keep the copper area small. optimal, slowing down the gate drive slightly can be helpful to reduce noise and ringing.
PAGE 27
Data Sheet ADP1850 TYPICAL OPERATING CIRCUITS 330pF 42.2kΩ 47pF VIN = 10V TO 18V M1 CIN 45.3kΩ 187kΩ 22pF CIN1 100nF VCCO L1 2.1kΩ 2Ω VCCO 25 BST1 4 26 ILIM1 VIN 27 PGOOD1 3 28 SS1 SYNC 29 RAMP1 2 30 FB1 EN1 31 COMP1 1 32 TRK1 10kΩ 0.1µF COUT11 COUT12 VOUT1 3.3V 14A M2 SW1 24 DH1 23 1µF 22kΩ PGND1 22 1µF DL1 21 1µF 2Ω ADP1850 EN2 SW2 17 11 12 13 187kΩ 10 VCCO 15 16 L2 M4 COUT21 0.1µF COUT22 VOUT2 1.8V 14A 100nF TO VIN 10kΩ CIN2 2.
PAGE 28
ADP1850 Data Sheet 560pF 28kΩ 33pF VIN = 10V TO 20V M1A 73.2kΩ 150kΩ CIN1 100nF VCCO L1 2.8kΩ 2Ω VCCO 25 ILIM1 4 26 BST1 VIN 27 PGOOD1 3 28 SS1 SYNC 29 RAMP1 2 30 COMP1 EN1 31 FB1 1 32 TRK1 10kΩ 0.1µF COUT1 VOUT1 5V 5A M1B SW1 24 DH1 23 1µF 22kΩ PGND1 22 1µF DL1 21 1µF 2Ω ADP1850 VIN DL2 20 5 VDL 6 AGND PGND2 19 7 FREQ DH2 18 8 EN2 SW2 17 M2A CIN2 VCCO ILIM2 BST2 12 13 14 15 16 10kΩ 10kΩ fSW = 750kHz, PULSE SKIP MODE M2B 0.
PAGE 29
Data Sheet ADP1850 1.8nF 5.34kΩ 33pF VIN = 3V TO 5.5V M1 7.5kΩ 20kΩ CIN1 100nF VCCO L1 4.99kΩ 5Ω 3 VIN 4 VCCO FB1 COMP1 RAMP1 28 27 26 25 BST1 SYNC 29 ILIM1 2 30 SS1 EN1 31 PGOOD1 1 32 TRK1 10kΩ 0.1µF COUT1 VOUT1 1.05V 1.8A M2 SW1 24 DH1 23 1µF 47kΩ PGND1 22 1µF DL1 21 1µF ADP1850 VIN DL2 20 5 VDL 6 AGND PGND2 19 7 FREQ DH2 18 8 EN2 SW2 17 M3 CIN2 SS2 12 13 8.
PAGE 30
ADP1850 Data Sheet 3.3nF 8.87kΩ VIN = 10V TO 14V 180pF CIN 8.3kΩ CIN11 22pF 137kΩ M1 M2 CIN12 100nF TO VCCO 10kΩ L1 2Ω BST1 VCCO 25 ILIM1 4 26 PGOOD1 VIN 27 SS1 3 28 RAMP1 SYNC 29 COMP1 EN1 2 30 FB1 1 31 TRK1 1.74kΩ 32 0.1µF COUT11 M3 SW1 COUT12 M4 24 DH1 23 1µF 22kΩ PGND1 22 DL1 21 EN2 SW2 17 9 10 11 12 13 14 15 16 CIN21 TO VCCO TO FB1 TO TO VIN SS1 M5 M6 22pF CIN22 L2 1.74kΩ 0.
PAGE 31
Data Sheet ADP1850 OUTLINE DIMENSIONS 0.30 0.25 0.18 32 25 0.50 BSC 0.80 0.75 0.70 0.50 0.40 0.30 8 16 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 3.65 3.50 SQ 3.45 EXPOSED PAD 17 TOP VIEW PIN 1 INDICATOR 1 24 9 BOTTOM VIEW 0.25 MIN 3.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WHHD. 04-02-2012-A PIN 1 INDICATOR 5.10 5.00 SQ 4.90 Figure 48.