Datasheet

ADP1829 Data Sheet
Rev. C | Page 8 of 28
Pin No. Mnemonic Description
23 BST1 Boost Capacitor Input for Channel 1. Powers the high-side gate driver DH1. Connect a 0.22 μF to 0.47 μF
ceramic capacitor from BST1 to SW1 and a Schottky diode from PV to BST1.
24 POK1 Open-Drain Power OK Output for Channel 1. Sinks current when FB1 is out of regulation. Connect a pull-up
resistor from POK1 to VREG.
25
EN1
Enable Input for Channel 1. Drive EN1 high to turn on the Channel 1 controller, and drive it low to turn off.
Enabling starts the internal LDO. Tie to IN for automatic startup.
26 EN2 Enable Input for Channel 2. Drive EN2 high to turn on the Channel 2 controller, and drive it low to turn off.
Enabling starts the internal LDO. Tie to IN for automatic startup.
27 LDOSD LDO Shut-Down Input. Only used to shut down the LDO in those applications where IN is tied directly to VREG.
Otherwise, connect LDOSD to GND or leave it open, as it has an internal 100 kΩ pull-down resistor.
28 IN Input Supply to the Internal Linear Regulator. Drive IN with 5.5 V to 20 V to power the ADP1829 from the LDO.
For input voltages between 3.0 V and 5.5 V, tie IN to VREG and PV.
29 VREG Output of the Internal Linear Regulator (LDO). The internal circuitry and gate drivers are powered from VREG.
Bypass VREG to ground plane with 1 μF ceramic capacitor.
30 SS1 Soft Start Control Input. Connect a capacitor from SS1 to GND to set the soft start period.
31
TRK1
Tracking Input for Channel 1. To track a master voltage, drive TRK1 from a voltage divider to the master voltage.
If the tracking function is not used, connect TRK1 to VREG.
32 COMP1 Error Amplifier Output for Channel 1. Connect an RC network from COMP1 to FB1 to compensate Channel 1.
EPAD The exposed pad must be connected to AGND.