Datasheet

ADP1829 Data Sheet
Rev. C | Page 6 of 28
FUNCTIONAL BLOCK DIAGRAM
IN
UVLO
LOGIC
SYNC
FREQ
LINEAR REG
REF
PV
LDOSD
VREG
VREG
QS
R
PWM
PV
GND
+
–
+
–
+
–
+
+
+
–
+
–
+
–
+
–
+
–
+
–
+
+
+
–
VREG
THERMAL
SHUTDOWN
0.75V
0.55V
0.6V
0.8V
ILIM2
CK1
FAULT2FAULT1
50µA
Q
QS
R
PWM
Q
ILIM1
CK1
RAMP1
CK2
RAMP2
OSCILLATOR
PHASE 1 = 0°
PHASE 2 = 180°
BST1
DH1
SW1
DL1
PGND1
CSL1
POK1
BST2
DH2
SW2
DL2
PGND2
CSL2
POK2
VREG
EN1
EN2
COMP1
FB1
TRK1
SS1
COMP2
FB2
TRK2
UV2
SS2
0.6V
0.8V
FAULT1
0.6V
0.8V
FAULT2
RAMP1
0.75V
0.55V
RAMP2
0.75V
0.55V
VREG
ILIM2
50µA
CK2
ADP1829
BOTTOM PADDLE
OF LFCSP
06784-002
Figure 2.