Datasheet

Data Sheet ADP1829
Rev. C | Page 19 of 28
COMPENSATING THE VOLTAGE MODE BUCK
REGULATOR
Assuming the LC filter design is complete, the feedback control
system can then be compensated. Good compensation is critical
to proper operation of the regulator. Calculate the quantities in
Equation 19 through Equation 47 to derive the compensation
values. The goal is to guarantee that the voltage gain of the buck
converter crosses unity at a slope that provides adequate phase
margin for stable operation. Additionally, at frequencies above
the crossover frequency, f
CO
, guaranteeing sufficient gain
margin and attenuation of switching noise are important
secondary goals. For initial practical designs, a good choice for
the crossover frequency is 1/10 of the switching frequency, so
first calculate
10
SW
CO
f
f 
(19)
This gives sufficient frequency range to design a compensation
that attenuates switching artifacts, while also giving sufficient
control loop bandwidth to provide good transient response.
The output LC filter is a resonant network that inflicts two poles
upon the response at a frequency f
LC
, so next calculate
LCπ
f
LC
2
1

(20)
Generally speaking, the LC corner frequency is about two
orders of magnitude below the switching frequency, and
therefore, about one order of magnitude below crossover. To
achieve sufficient phase margin at crossover to guarantee
stability, the design must compensate for the two poles at the
LC corner frequency with two zeros to boost the system phase
prior to crossover. The two zeros require an additional pole or
two above the crossover frequency to guarantee adequate gain
margin and attenuation of switching noise at high frequencies.
Depending on component selection, one zero might already be
generated by the equivalent series resistance (ESR) of the output
capacitor. Calculate this zero corner frequency, f
ESR
, as
OUT
ESR
ESR
CRπ
f
2
1
 (21)
Figure 26 shows a typical Bode plot of the LC filter by itself.
The gain of the LC filter at crossover can be linearly approxi-
mated from Figure 26 as
ESRLC
FILTER
AAA 


















ESR
CO
LC
ESR
FILTER
f
f
f
f
A logdB20logdB40 (22)
If f
ESR
≈ f
CO
, then add another 3 dB to account for the local
difference between the exact solution and the linear approxima-
tion in Equation 22.
0dB
GAIN
FREQUENCY
LC FILTER BODE PLOT
PHASE
f
LC
f
ESR
f
CO
f
SW
A
FILTER
–40dB/dec
Φ
FILTER
0°
–90°
–180°
–20dB/dec
06784-025
Figure 26. LC Filter Bode Plot
To compensate the control loop, the gain of the system must be
brought back up so that it is 0 dB at the desired crossover
frequency. Some gain is provided by the PWM modulation itself.









RAMP
IN
MOD
V
V
A log20 (23)
For systems using the internal oscillator, this becomes









V
V
A
IN
MOD
3.1
log20 (24)
Note that if the converter is being synchronized, the ramp
voltage, V
RAMP
, is lower than 1.3 V by the percentage of
frequency increase over the nominal setting of the FREQ pin.









SYNC
FREQ
RAMP
f
f
V
2
V3.1
(25)
The factor of 2 in the numerator takes into account that the
SYNC frequency is divided by 2 to generate the switching
frequency. For example, if the FREQ pin is set high for the
600 kHz range and a 2 MHz SYNC signal is applied, the ramp
voltage is 0.78 V. This increases the gain of the modulator by
4.4 dB in this example.