Datasheet

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Dual, Interleaved, Step-Down

DC-to-DC Controller with Tracking

Data Sheet

ADP1829

Rev. C Document Feedback

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FEATURES

Fixed frequency operation: 300 kHz, 600 kHz, or

synchronized operation up to 1 MHz

Supply input range: 3.0 V to 20 V

Wide power stage input range: 1 V to 24 V

Interleaved operation results in smaller, low cost

input capacitor

All-N-channel MOSFET design for low cost

±0.85% accuracy at 0

C to 70

Soft start, thermal overload, current-limit protection

10 µA shutdown supply current

Internal linear regulator

Lossless R

DSON

current-limit sensing

Reverse current protection during soft start for handling

precharged outputs

Independent Power OK outputs

Voltage tracking for sequencing or DDR termination

Available in 5 mm × 5 mm, 32-lead LFCSP

APPLICATIONS

Telecommunications and networking systems

Medical imaging systems

Base station power

Set-top boxes

Printers

DDR termination

TYPICAL APPLICATION CIRCUIT

GND

EN1

EN2

BST2

SW2

DH2

CSL2

DL2

PGND2

FB2

COMP2

FREQ

LDOSD

SYNC

TRK1

TRK2

VREG

BST1

DH1

SW1

CSL1

DL1

PGND1

FB1

COMP1

ADP1829

180µF

3900pF

390pF

IRFR3709Z

IRLR7807Z

1.2V,

1.8V,

390pF

3900pF

= 12V

560µF

2.2µH 2.2µH

1µF

0.47µF

4.53kΩ

1kΩ

2kΩ

2kΩ 2kΩ

06784-001

Figure 1.

GENERAL DESCRIPTION

The ADP1829 is a versatile, dual, interleaved, synchronous

PWM buck controller that generates two independent output

rails from an input of 3.0 V to 20 V, with power input voltage

ranging from 1.0 V to 24 V. Each controller can be configured

to provide output voltages from 0.6 V to 85% of the input

voltage and is sized to handle large MOSFETs for point-of-load

regulators. The two channels operate 180° out of phase,

reducing stress on the input capacitor and allowing smaller, low

cost components. The ADP1829 is ideal for a wide range of

high power applications, such as DSP and processor core I/O

power, and general-purpose power in telecommunications,

medical imaging, PC, gaming, and industrial applications.

The ADP1829 operates at a pin-selectable, fixed switching

frequency of either 300 kHz or 600 kHz, minimizing external

component size and cost. For noise-sensitive applications, it can

also be synchronized to an external clock to achieve switching

frequencies between 300 kHz and 1 MHz. The ADP1829

includes soft start protection to prevent inrush current from the

input supply during startup, reverse current protection during

soft start for precharged outputs, as well as a unique adjustable

lossless current-limit scheme utilizing external MOSFET sensing.

For applications requiring power supply sequencing, the

ADP1829 also provides tracking inputs that allow the output

voltages to track during startup, shutdown, and faults. This

feature can also be used to implement DDR memory bus

termination.

The ADP1829 is specified over the −40°C to +125°C junction

temperature range and is available in a 32-lead LFCSP package.

Summary of content (28 pages)

PAGE 1
Dual, Interleaved, Step-Down DC-to-DC Controller with Tracking ADP1829 Data Sheet FEATURES TYPICAL APPLICATION CIRCUIT Fixed frequency operation: 300 kHz, 600 kHz, or synchronized operation up to 1 MHz Supply input range: 3.0 V to 20 V Wide power stage input range: 1 V to 24 V Interleaved operation results in smaller, low cost input capacitor All-N-channel MOSFET design for low cost ±0.
PAGE 2
ADP1829 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Tracking ....................................................................................... 14 Applications ....................................................................................... 1 MOSFET Drivers ........................................................................ 15 Typical Application Circuit .........................................
PAGE 3
Data Sheet ADP1829 SPECIFICATIONS IN = 12 V, ENx = FREQ = PV = VREG = 5 V, SYNC = GND, TJ = −40°C to +125°C, unless otherwise specified. All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). Typical values are at TA = 25°C. Table 1.
PAGE 4
ADP1829 Parameter OSCILLATOR Oscillator Frequency SYNC Synchronization Range 2 SYNC Minimum Input Pulse Width CURRENT SENSE CSL1, CSL2 Threshold Voltage CSL1, CSL2 Output Current Current Sense Blanking Period GATE DRIVERS DH1, DH2 Rise Time DH1, DH2 Fall Time DL1, DL2 Rise Time DL1, DL2 Fall Time DH to DL, DL to DH Dead Time LOGIC THRESHOLDS SYNC, FREQ, LDOSD Input High Voltage SYNC, FREQ, LDOSD Input Low Voltage SYNC, FREQ Input Leakage Current LDOSD Pull-Down Resistance EN1, EN2 Input High Voltage EN1, EN
PAGE 5
Data Sheet ADP1829 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter IN, EN1, EN2 BST1, BST2 BST1, BST2 to SW1, SW2 CSL1, CSL2 SW1, SW2 DH1 DH2 DL1, DL2 to PGND PGND to GND LDOSD, SYNC, FREQ, COMP1, COMP2, SS1, SS2, FB1, FB2, VREG, PV, POK1, POK2, TRK1, TRK2 θJA 4-Layer (JEDEC Standard Board) 1, 2 Operating Ambient Temperature Operating Junction Temperature 3 Storage Temperature Rating −0.3 V to +20.5 V −0.3 V to +30 V −0.3 V to +6 V −1 V to +30 V −2 V to +30 V SW1 − 0.3 V to BST1 + 0.3 V SW2 − 0.
PAGE 6
ADP1829 Data Sheet FUNCTIONAL BLOCK DIAGRAM IN ADP1829 VREG LINEAR REG 0.6V 0.8V 0.75V REF 0.55V THERMAL SHUTDOWN UVLO VREG VREG BST1 LDOSD ILIM2 EN1 DH1 CK1 LOGIC S Q SW1 PWM EN2 FAULT1 R FAULT2 PV Q CK1 FREQ SYNC DL1 RAMP1 OSCILLATOR PHASE 1 = 0° PHASE 2 = 180° VREG + ILIM1 CK2 50µA PGND1 – CSL1 RAMP2 RAMP1 + POK1 – COMP1 FB1 TRK1 0.6V – + + + 0.75V + – BST2 + SS1 0.8V 0.55V DH2 – S CK2 FAULT1 Q PWM RAMP2 + R Q – COMP2 FB2 TRK2 0.6V – + + + 0.
PAGE 7
Data Sheet ADP1829 32 31 30 29 28 27 26 25 COMP1 TRK1 SS1 VREG IN LDOSD EN2 EN1 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 PIN 1 INDICATOR ADP1829 TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 POK1 BST1 DH1 SW1 CSL1 PGND1 DL1 PV NOTES 1. THE EXPOSED PAD MUST BE CONNECTED TO AGND. 06784-003 SS2 POK2 BST2 DH2 SW2 CSL2 PGND2 DL2 9 10 11 12 13 14 15 16 FB1 SYNC FREQ GND UV2 FB2 COMP2 TRK2 Figure 3. Pin Configuration Table 3. Pin Function Descriptions Pin No.
PAGE 8
ADP1829 Pin No. 23 Mnemonic BST1 24 POK1 25 EN1 26 EN2 27 LDOSD 28 IN 29 VREG 30 31 SS1 TRK1 32 COMP1 EPAD Data Sheet Description Boost Capacitor Input for Channel 1. Powers the high-side gate driver DH1. Connect a 0.22 μF to 0.47 μF ceramic capacitor from BST1 to SW1 and a Schottky diode from PV to BST1. Open-Drain Power OK Output for Channel 1. Sinks current when FB1 is out of regulation. Connect a pull-up resistor from POK1 to VREG. Enable Input for Channel 1.
PAGE 9
Data Sheet ADP1829 TYPICAL PERFORMANCE CHARACTERISTICS 95 92 VIN = 5V SWITCHING FREQUENCY = 300kHz VIN = 12V 90 90 85 EFFICIENCY (%) EFFICIENCY (%) 88 VIN = 20V VIN = 15V 80 86 84 SWITCHING FREQUENCY = 600kHz 82 75 0 5 10 15 20 LOAD CURRENT (A) 78 06784-004 70 0 5 10 20 15 LOAD CURRENT (A) Figure 4. Efficiency vs. Load Current, VOUT = 1.8 V, 300 kHz Switching 06784-007 80 Figure 7. Efficiency vs. Load Current, VIN = 12 V, VOUT = 1.8 V 95 4.980 VOUT = 3.3V 90 4.
PAGE 10
ADP1829 Data Sheet 4.960 0.6010 0.6005 FEEDBACK VOLTAGE (V) 4.952 4.948 4.944 0.6000 0.5995 0.5990 0.5985 20 0 60 40 80 100 LOAD CURRENT (mA) 0.5980 –40 06784-010 4.940 60 35 10 –15 85 TEMPERATURE (°C) Figure 10. VREG vs. Load Current, VIN = 12 V 06784-013 VREG (V) 4.956 Figure 13. Feedback Voltage vs.
PAGE 11
Data Sheet ADP1829 T EXTERNAL CLOCK, FREQUENCY = 1MHz T VOUT1, AC-COUPLED, 100mV/DIV SW PIN, CHANNEL 1 LOAD ON 100µs/DIV 400ns/DIV Figure 19. Out-of-Phase Switching, External 1 MHz Clock Figure 16. 1.5 A to 15 A Load Transient Response, VIN = 12 V T 06784-019 SW PIN, CHANNEL 2 LOAD OFF 06784-016 LOAD OFF T SS1, 0.5V/DIV VOUT1, 0.5V/DIV EXTERNAL CLOCK, FREQUENCY = 2MHz SW PIN, CHANNEL 1 INPUT CURRENT, 0.
PAGE 12
ADP1829 Data Sheet T VIN, 5V/DIV EN2 PIN, 5V/DIV VOUT2, 2V/DIV VOUT, 2V/DIV EN1 = 5V Figure 22. Power-On Response, EN Tied to IN TRACK PIN VOLTAGE, 200mV/DIV Figure 24. Coincident Voltage Tracking Response T 06784-023 FEEDBACK PIN VOLTAGE, 200mV/DIV 20ms/DIV 40ms/DIV Figure 23. Output Voltage Tracking Response Rev.
PAGE 13
Data Sheet ADP1829 THEORY OF OPERATION The ADP1829 is a dual, synchronous, PWM buck controller capable of generating output voltages down to 0.6 V and output currents in the tens of amps. The switching of the regulators is interleaved for reduced current ripple. It is ideal for a wide range of applications, such as DSP and processor core I/O supplies, general-purpose power in telecommunications, medical imaging, gaming, PCs, set-top boxes, and industrial controls.
PAGE 14
ADP1829 Data Sheet If FREQ is driven low, the recommended SYNC input frequency is between 600 kHz and 1.2 MHz. If FREQ is driven high, the recommended SYNC frequency is between 1.2 MHz and 2 MHz. The FREQ setting should be carefully observed for these SYNC frequency ranges, as the PWM voltage ramp scales down from about 1.3 V based on the percentage of frequency overdrive.
PAGE 15
Data Sheet ADP1829 MOSFET DRIVERS CURRENT LIMIT The DH1 and DH2 pins drive the high-side switch MOSFETs. These are boosted 5 V gate drivers that are powered by bootstrap capacitor circuits. This configuration allows the highside, N-channel MOSFET gate to be driven above the input voltage, allowing full enhancement and a low voltage drop across the MOSFET. The bootstrap capacitors are connected from the SW pins to their respective BST pins.
PAGE 16
ADP1829 Data Sheet APPLICATIONS INFORMATION SELECTING THE INPUT CAPACITOR Choose the inductor value using the equation The input current to a buck converter is a pulse waveform. It is zero when the high-side switch is off and approximately equal to the load current when it is on. The input capacitor carries the input ripple current, allowing the input power source to supply only the dc current.
PAGE 17
Data Sheet ADP1829 In the case of output capacitors where the impedance of the ESR and ESL are small at the switching frequency, for instance, where the output capacitor is a bank of parallel MLCC capacitors, the capacitive impedance dominates and the ripple equation reduces to ∆VOUT ≈ ∆I L 8 C OUT f SW (7) Make sure that the ripple current rating of the output capacitors is greater than the maximum inductor ripple current.
PAGE 18
ADP1829 Data Sheet SETTING THE CURRENT LIMIT VIN ADP1829 The current-limit comparator measures the voltage across the low-side MOSFET to determine the load current. Because the CSL current and the MOSFET RDSON vary over process and temperature, the minimum current limit should be set to ensure that the system can handle the maximum desired load current.
PAGE 19
Data Sheet ADP1829 LC FILTER BODE PLOT COMPENSATING THE VOLTAGE MODE BUCK REGULATOR GAIN Assuming the LC filter design is complete, the feedback control system can then be compensated. Good compensation is critical to proper operation of the regulator. Calculate the quantities in Equation 19 through Equation 47 to derive the compensation values. The goal is to guarantee that the voltage gain of the buck converter crosses unity at a slope that provides adequate phase margin for stable operation.
PAGE 20
ADP1829 Data Sheet The rest of the system gain is needed to reach 0 dB at crossover. The total gain of the system, therefore, is given by GAIN (26) where: AMOD is the gain of the PWM modulator. AFILTER is the gain of the LC filter including the effects of the ESR zero. ACOMP is the gain of the compensated error amplifier. PHASE 0° Φ1 –90° Φ2 Figure 27.
PAGE 21
Data Sheet ADP1829 Type II Compensator Next choose the high frequency pole, fP1, to be 1/2 of fSW. LO PE –1 S fZ PHASE LO PE 2 –270° CHF (37) 2R Z C HF Solving for CHF in Equation 36 and Equation 37 yields CI C HF  RTOP EA VRAMP VREF 0V 1 (38) f SW R Z Type III Compensator TO PWM COMP 06784-027 RBOT (36) 1 f P1  RZ f SW Because CHF << CI, Equation 29 is simplified to fP –180° FROM VOUT 1 f P1  –1 S G (dB) LO S +1 PE LO PE –1 SL O Figure 28.
PAGE 22
ADP1829 Data Sheet t  VCSS  0.8 V 1  e RC SS   Because of the finite output current drive of the error amplifier, CI needs to be less than 10 nF. If it is larger than 10 nF, choose a larger RTOP and recalculate RZ and CI until CI is less than 10 nF. Because CHF << CI, combining Equation 29 and Equation 39 yields 1 πf SW R Z The soft start period ends when the voltage on the soft start pin reaches 0.6 V. Substituting 0.
PAGE 23
Data Sheet ADP1829 COINCIDENT TRACKING The most common application is coincident tracking, used in core vs. I/O voltage sequencing and similar applications. Coincident tracking limits the slave output voltage to be the same as the master voltage until it reaches regulation. Connect the slave TRK input to a resistor divider from the master voltage that is the same as the divider used on the slave FB pin. This forces the slave voltage to be the same as the master voltage.
PAGE 24
ADP1829 Data Sheet Setting the Channel 2 Undervoltage Threshold for Ratiometric Tracking THERMAL CONSIDERATIONS If FB2 is regulated to a voltage lower than 0.6 V by configuring TRK2 for ratiometric tracking, the Channel 2 undervoltage threshold can be set appropriately by splitting the top resistor in the voltage divider, as shown in Figure 33.
PAGE 25
Data Sheet ADP1829 PCB LAYOUT GUIDELINES For PCB layout guidelines, refer to the AN-1119 Application Note, Printed Circuit Board Layout Guidelines for Step-Down Regulators, Optimizing for Low Noise Design with Dual Channel Switching Controllers. LFCSP PACKAGE CONSIDERATIONS The LFCSP package has an exposed die paddle on the bottom that efficiently conducts heat to the PCB. The thermal pad of the LFCSP package provides a low thermal impedance path to the PCB.
PAGE 26
ADP1829 Data Sheet APPLICATION CIRCUITS are the polymer aluminum capacitors that are available from other manufacturers such as United Chemi-con. Aluminum electrolytic capacitors, such as Rubycon’s ZLG low ESR series, can also be paralleled up at the input or output to meet the ripple current requirement.
PAGE 27
Data Sheet ADP1829 package, which reduces cost and saves layout space. An alternative to using the dual-channel SO-8 package is using two single MOSFETs in SOT-23 or TSOP-6 packages, which are low cost and small in size. The ADP1829 can also be configured to drive an output load of less than 1 A. Figure 35 shows a typical application circuit that drives 1.5 A and 3 A loads in all multilayer ceramic capacitor (MLCC) solutions.
PAGE 28
ADP1829 Data Sheet OUTLINE DIMENSIONS 5.00 BSC SQ 0.60 MAX 0.60 MAX 25 32 1 24 0.50 BSC 3.25 3.10 SQ 2.95 EXPOSED PAD 17 TOP VIEW 1.00 0.85 0.80 SEATING PLANE 12° MAX 0.80 MAX 0.65 TYP 0.50 0.40 0.30 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 0.30 0.25 0.18 8 16 9 BOTTOM VIEW 0.25 MIN 3.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 05-23-2012-A 4.