Datasheet

ADP1828
Rev. C | Page 27 of 36
A more accurate solution is to provide a divider from the
master voltage that sets the TRK pin voltage to be something
lower than 0.6 V at regulation, for example, 0.5 V. The slave
channel can be viewed as having a 0.5 V external reference
supplied by the master voltage. Keep in mind that PGOOD
is tripped when the TRK voltage is set to less than 0.55 V.
Once this is complete, the FB divider for the slave voltage is
designed as in the Compensating the Voltage Mode Buck
Regulator section except to substitute the 0.5 V reference
for the V
FB
voltage. The ratio of the slave output voltage to
the master voltage is a function of the two dividers:
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
+
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
+
=
TRKB
TRKT
BOT
TOP
MASTER
OUT
R
R
R
R
V
V
1
1
(51)
Figure 47 shows an example of ratiometric tracking circuit and
Figure 48 shows its voltage tracking waveforms.
FB
TRK
SS
R
TRKB
10kΩ
R
TRKT
49.9kΩ
0.55V
ADP1828
OR
ADP1829
FB
POWER
COMPONENTS
POWER
COMPONENTS
ADP1828
EN
EN
SS
R
TOP
22.6kΩ
R
BOT
10kΩ
C
SS
1µF
C
SS
150nF
3.3V
V
OUT_MASTER
1.8V
V
OUT_SLAVE
0
6865-048
Figure 47. An Example of a Ratiometric Tracking Circuit
CH1 5.00V
CH3 1.00V
CH2 1.00V M 100ms A CH1 2.60V
1
4
CH4 1.00V
V
OUT_MASTER
EN FOR BOTH ADP1828
V
OUT_SLAVE
TRK_SLAVE
B
W
B
W
B
W
06865-049
Figure 48. Ratiometric Tracking of Figure 47
Another option is to add another tap to the divider for the
master voltage. Split the R
BOT
resistor of the master voltage into
two pieces, with the new tap at 0.5 V when the master voltage is
in regulation. This saves one resistor, but be aware that Type III
compensation on the master voltage causes the feedforward
signal of the master voltage to appear at the TRK input of the
slave channel.
Figure 49 shows an example of DDR memory termination
application circuit, where the DDR memory termination voltage,
VTT, is ½ of VDDQ. VTT can sink current during the off cycle
of the ADP1828. The output waveform in Figure 50 shows that
VTT changes by one-half of the output change in VDDQ.
FB
TRK
SS
R
TRKB
10kΩ
R
TRKT
40.2kΩ
0.5V
ADP1828
OR
ADP1829
FB
POWER
COMPONENTS
POWER
COMPONENTS
ADP1828
EN
EN
SS
R
TOP
15kΩ
R
BOT
10kΩ
C
SS
1µF
C
SS
150nF
2.5V
VDDQ
1.25V
VTT
06865-050
Figure 49. An Example of a DDR Termination Circuit
CH1 500mV
CH3 500mV
CH2 100mV M 200µs A CH1 50.0mV
3
2
1
VDDQ (2.5V ± 0.25V, AC-COUPLED)
VTT (1.25V ± 0.125V, AC-COUPLED)
TRK
B
W
B
W
B
W
T
06865-051
Figure 50. DDR Termination; Output Waveforms of Figure 49
In addition, by selecting the resistor values in the divider carefully,
Equation 51 shows that the slave voltage output can be made to
have a faster ramp rate than that of the master voltage by setting
the TRK voltage at the slave larger than 0.6 V and R
TRKB
greater
than R
TRKT
. Make sure that the master SS period is long enough
(that is, use a sufficiently large SS capacitor) such that the input
inrush current does not run into the current limit of the power
supply during startup.
CH1 5.00V
CH3 1.00V
CH2 1.00V M 100ms A CH1 2.60V
1
4
CH4 1.00V
V
OUT_MASTER
EN FOR BOTH ADP1828
TRK_SLAVE
B
W
B
W
B
W
V
OUT_SLAVE
0
6865-052
Figure 51. Ratiometric Tracking of Figure 47 with R
TRKT
= 5 kΩ