Datasheet

ADP1828
Rev. C | Page 22 of 36
Depending on component selection, one zero might already be
generated by the ESR of the output capacitor. Calculate this zero
corner frequency, f
ESR
, as
OUT
ESR
ESR
CRπ
f
2
1
=
(18)
Figure 37 shows a typical Bode plot of the LC filter by itself.
The gain of the LC filter at crossover can be linearly
approximated from Figure 37 as
ESRLC
FILTER
AAA +=
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
×−
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
×−=
ESR
CO
LC
ESR
FILTER
f
f
f
f
A
logdB20logdB40 (19)
If
f
ESR
≈ f
CO
, then add another 3 dB to account for the local
difference between the exact solution and the linear approxi-
mation in Equation 19.
0dB
GAIN
FREQUENCY
PHASE
f
LC
f
ESR
f
CO
f
SW
A
FILTER
–40dB/dec
Φ
FILTER
0°
–90°
–180°
–20dB/dec
06865-038
Figure 37. LC Filter Bode Plot
To compensate the control loop, the gain of the system must
be brought back up so that it is 0 dB at the desired crossover
frequency. Some gain is provided by the PWM modulation itself.
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
=
RAMP
IN
MOD
V
V
A log20
(20)
For systems using the internal oscillator, this becomes
(21)
Note that if the converter is being synchronized, the ramp
voltage, V
RAMP
, is lower than 1.0 V by the percentage of
frequency increase over the nominal setting of the FREQ pin:
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
=
V0.1
log20
IN
MOD
V
A
⎟
⎟
⎠
⎞
⎜
⎜
⎛
=
FREQ
RAMP
f
V V0.1
⎝
SYNC
f
(22)
For example, if FREQ is grounded or connected to VREG, then
f
FREQ
is 300 kHz or 600 kHz, respectively. If the frequency is set
by a resistor, then f
FREQ
is 300 kHz and f
SYNC
is the frequency set
by the resistor. V
RAMP
is greater than 1.0 V if f
SYNC
is less than
f
FREQ
. The rest of the system gain needs to reach 0 dB at cross-
over. The total gain of the system, therefore, is given by
A
T
= A
MOD
+ A
FILTER
+ A
COMP
(23)
where:
A
MOD
is the gain of the PWM modulator.
A
FILTER
is the gain of the LC filter including the effects of
the ESR zero.
A
COMP
is the gain of the compensated error amplifier.
Additionally, the phase of the system must be brought back
up to guarantee stability. Note from the Bode plot of the filter
that the LC contributes −180° of phase shift (see Figure 37).
Because the error amplifier is an integrator at low frequency,
it contributes an initial −90°. Therefore, before adding com-
pensation or accounting for the ESR zero, the system is already
down −270°. To avoid loop inversion at crossover, or −180°
phase shift, a good initial practical design is to require a phase
margin of 60°, which is therefore an overall phase loss of −120°
from the initial low frequency dc phase. The goal of the com-
pensation is to boost the phase back up from −270° to −120°
at crossover.
Two common compensation schemes are used, which are
sometimes referred to as Type II or Type III compensation,
depending on whether the compensation design includes
two or three poles (see the Type II Compensator and Type III
Compensator sections). Dominant-pole compensation, or
single-pole compensation, is referred to as Type I compensation,
but it is not very useful for dealing successfully with switching
regulators.
If the zero produced by the ESR of the output capacitor provides
sufficient phase boost at crossover, Type II compensation is
adequate. If the phase boost produced by the ESR of the output
capacitor is not sufficient, another zero is added to the compen-
sation network, and thus Type III is used.
In Figure 38, the location of the ESR zero corner frequency
gives a significantly different net phase at the crossover
frequency.