Datasheet

ADP1828
Rev. C | Page 21 of 36
SETTING THE CURRENT LIMIT
The current-limit comparator measures the voltage across the
low-side MOSFET to determine the load current.
The current limit is set through the current-limit resistor, R
CL
.
The current sense pin, CSL, sources 50 A through the external
current-limit setting resistor, R
CL
. This creates an offset voltage
of R
CL
multiplied by the 50 A CSL current. When the drop
across the low-side MOSFET R
DSON
is equal to or greater than
this offset voltage, the ADP1828 flags a current-limit event.
Because the CSL current and the MOSFET R
DSON
vary over
process and temperature, the minimum current limit should be
set to ensure that the system can handle the maximum desired
load current. To do this, use the peak current in the inductor,
which is the desired current-limit level plus the ripple current,
the maximum R
DSON
of the MOSFET at its highest expected
temperature, and the minimum CSL current:
A
RI
R
MAXDSON
LPK
CL
μ
−
=
42
mV38
)(
(14)
where:
I
LPK
is the peak inductor current.
−38 mV is the CSL threshold voltage.
Because the buck converters are usually running a fairly high
current, PCB layout and component placement may affect the
current-limit setting. An iteration of the R
CL
value may be required
for a particular board layout and MOSFET selection. If alternate
MOSFETs are substituted at some point in production, these
resistor values may also need an iteration.
ACCURATE CURRENT-LIMIT SENSING
The R
DSON
of the external low-side MOSFET can vary by more
than 50% over the temperature range. Accurate current-limit
sensing can be achieved by adding a current sense resistor from
the source of the low-side MOSFET to PGND. Make sure that
the power rating of the current sense resistor is adequate for
the application. Apply Equation 14 to calculate R
CL
and replace
R
DSON(MAX)
with R
SENSE
.
ADP1828
V
IN
M2
M1
L
DH
DL
CSL
C
OUT
V
OUT
R
CL
R
SENSE
06865-037
Figure 36. Accurate Current-Limit Sensing
FEEDBACK VOLTAGE DIVIDER
The output regulation voltage is set through the feedback volt-
age divider. The output voltage is divided down through the
voltage divider and drives the FB feedback input. The regulation
threshold at FB is 0.6 V. The maximum input bias current into
FB is 100 nA. For a 0.15% degradation in regulation voltage and
with 100 nA bias current, the low-side resistor, R
BOT
, needs to be
less than 9 kΩ, which results in 67 µA of divider current. For
R
BOT
, use a 1 k to 10 k resistor. A larger value resistor can be
used, but results in a reduction in output voltage accuracy due
to the input bias current at the FB pin, while lower values cause
increased quiescent current consumption. Choose R
TOP
to set
the output voltage by using the following equation:
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
−
=
FB
FB
OUT
BOTTOP
V
VV
RR
(15)
where:
R
TOP
is the high-side voltage divider resistance.
R
BOT
is the low-side voltage divider resistance.
V
OUT
is the regulated output voltage.
V
FB
is the feedback regulation threshold, 0.6 V.
COMPENSATING THE VOLTAGE MODE BUCK
REGULATOR
Assuming the LC filter design is complete, the feedback control
system can then be compensated. Good compensation is critical
to proper operation of the regulator. Calculate the quantities in
Equation 16 through Equation 44 to derive the compensation
values. The goal is to guarantee that the voltage gain of the buck
converter crosses unity at a slope that provides adequate phase
margin for stable operation. Additionally, at frequencies above
the crossover frequency (f
CO
), guaranteeing sufficient gain margin
and attenuation of switching noise are important secondary
goals. For initial practical designs, a good choice for the
crossover frequency is one tenth of the switching frequency,
calculate first
10
SW
CO
f
f = (16)
This gives sufficient frequency range to design a compensation
scheme that attenuates switching artifacts, while also giving
sufficient control loop bandwidth to provide a good transient
response.
The output LC filter is a resonant network that inflicts two poles
upon the response at a frequency (f
LC
). Next, calculate
LCπ
f
LC
2
1
=
(17)
Generally speaking, the LC corner frequency is about two
orders of magnitude below the switching frequency, and
therefore about one order of magnitude below crossover.
To achieve sufficient phase margin at crossover to guarantee
stability, the design must compensate for the two poles at the
LC corner frequency with two zeros to boost the system phase
prior to crossover. The two zeros require an additional pole or
two above the crossover frequency to guarantee adequate gain
margin and attenuation of switching noise at high frequencies.