Datasheet

ADP1828
Rev. C | Page 17 of 36
The PV pin provides power to the low-side drivers. It is limited
to 5.5 V maximum input and should have a local decoupling
capacitor to PGND.
The synchronous rectifier is turned on for a minimum time
of about 200 ns on every switching cycle in order to sense the
current. This minimum off-time plus the nonoverlap dead time
puts a limit on the maximum high-side switch duty cycle based
on the selected switching frequency. Typically, this maximum
duty cycle is about 90% at 300 kHz switching. At 1.2 MHz
switching, it reduces to about 70% maximum duty cycle.
SETTING THE OUTPUT VOLTAGE
The output voltage is set using a resistive voltage divider from
the output to FB. The voltage divider splits the output voltage
to the 0.6 V FB regulation voltage to set the regulation output
voltage. The output voltage can be set to as low as 0.6 V and as
high as 85% of the power input voltage.
SWITCHING FREQUENCY CONTROL AND
SYNCHRONIZATION
The ADP1828 has a logic controlled frequency select input,
FREQ, which sets the switching frequency to 300 kHz or
600 kHz. Drive FREQ low at 300 kHz and high at 600 kHz.
The frequency can also be set to between 300 kHz and 600 kHz
by connecting a resistor between FREQ and GND. A 24.9 kΩ
sets the frequency to 600 kHz, 35.7 kΩ to 450 kHz, and 57.6 kΩ
to 300 kHz. Figure 34 shows f
OSC
as a function of R
FREQ
.
24000 29000 34000 39000 44000 49000 54000 59000
06865-034
OSCILLATOR FREQUENCY (kHz)
R
FREQ
(Ω)
200
250
300
350
400
450
500
550
600
T
A
= 25°C
V
IN
= 3V
V
IN
= 5V
Figure 34. f
OSC
vs. R
FREQ
The SYNC input is used to synchronize the converter switching
frequency to an external signal. This allows multiple ADP1828
converters to be operated at the same frequency to prevent
frequency beating or other interactions. The ADP1828 has a
clock output (CLKOUT), which can be used for synchronizing
the ADP1829 and other ADP1828 controllers, thus eliminating
the need for an external clock source. Pulling CLKSET low sets
the frequency at CLKOUT to 1× the internal oscillator frequency,
f
OSC
, and is 180° out of phase with f
OSC
. The 1× output is suitable
for synchronizing other ADP1828s. Setting CLKSET high
(connect to VREG) sets the frequency to 2× f
OSC
and is in phase
with f
OSC
. The 2× output is suitable for synchronizing the dual
channel ADP1829 controller (see Table 4).
Table 4. CLKOUT Truth Table
1
EN CLKSET SYNC CLKOUT Comment
H L H/L 1× f
OSC
180° out of phase with f
OSC
H H H/L 2× f
OSC
In phase with f
OSC
H X Clock in Clock
CLKOUT in-sync with
clock in
L X X L CLKOUT is low
1
X: don’t care, H: Logic high, L: Logic low.
To synchronize the ADP1828 switching frequency to an
external signal, drive the SYNC input with an external clock
or with the CLKOUT signal from another ADP1828. The
ADP1828 can be synchronized to between 1× and 2× the
internal oscillator frequency. If f
OSC
is set by R
FREQ
, then the
synchronization frequency range is from f
OSC
up to 600 kHz.
Driving SYNC faster than recommended for the FREQ setting
results in a small ramp signal, which could affect the signal-to-
noise ratio and the modulator gain and stability.
When an external clock is detected at the first SYNC edge, the
internal oscillator is reset and the clock control shifts to SYNC.
The SYNC edges then trigger subsequent clocking of the PWM
outputs. The high-side MOSFET turn-on follows the rising edge
of the sync input by approximately 320 ns (see Figure 35 for
an illustration). If the external SYNC signal disappears during
operation, the ADP1828 reverts to its internal oscillator and
experiences a delay of no more than a single cycle of the
internal oscillator.
SYNC
DH
DL
320ns
DT
DT (DEAD TIME) = 40ns
06865-035
Figure 35. Synchronization