Datasheet

ManualsBrandsANALOG DEVICES ManualsPMICsPMIC - voltage regulators - DC DC switch controllers QSOP 20

Synchronous Buck PWM,

Step-Down, DC-to-DC Controller

ADP1828

Rev. C

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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

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Tel: 781.329.4700 www.analog.com

FEATURES

Wide bias voltage range 3.0 V to 20 V

Wide power stage input range 1 V to 24 V

Wide output voltage range: 0.6 V to 85% of input voltage

±0.85% accuracy at 0

C to 70

All N-channel MOSFET design for low cost

Fixed-frequency operation at 300 kHz, 600 kHz, or resistor

adjustable 300 kHz to 600 kHz

Clock output for synchronizing other controllers

No current sense resistor required

Internal linear regulator

Voltage tracking for sequencing

Soft start and thermal overload protection

Overvoltage and undervoltage power-good indicator

15 μA shutdown supply current

Available in a 20-lead QSOP and 20-lead, 4mm × 4 mm LFCSP

APPLICATIONS

Telecom and networking systems

Base station power

Set-top boxes, game consoles

Printers and copiers

Medical imaging systems

DSP and microprocessor core power supplies

DDR termination

GENERAL DESCRIPTION

The ADP1828 is a versatile and synchronous PWM voltage

mode buck controller. It drives an all N-channel power stage

to regulate an output voltage as low as 0.6 V to 85% of the input

voltage and is sized to handle large MOSFETs for point-of-load

regulators. The ADP1828 is ideal for a wide range of high power

applications, such as DSP and processor core I/O power, and

general-purpose power in telecommunications, medical imaging,

PC, gaming, and industrial applications. It operates from input

bias voltages of 3 V to 20 V with an internal LDO that generates

a 5 V output for input bias voltages greater than 5.5 V.

The ADP1828 operates at a pin-selectable, fixed switching

frequency of either 300 kHz or 600 kHz, or at any frequency

between 300 kHz and 600 kHz with a resistor. The switching

frequency can also be synchronized to an external clock up to

2× the part’s nominal oscillator frequency. The clock output

can be used for synchronizing additional ADP1828s (or the

ADP1829 controllers), thus eliminating the need for an external

clock source. The ADP1828 includes soft start protection to

limit any inrush current from the input supply during startup,

reverse current protection during soft start for a precharged

output, as well as a unique adjustable lossless current-limit

scheme utilizing external MOSFET R

DSON

sensing.

For applications requiring power-supply sequencing, the

ADP1828 provides a tracking input that allows the output

voltage to track during startup, shutdown, and faults. The

additional supervisory and control features include thermal

overload, undervoltage lockout, and power good.

The ADP1828 operates over the −40°C to +125°C junction

temperature range and is available in a 20-lead QSOP and

20-lead, 4mm × 4mm LFCSP.

VREG

FREQ

SYNC

PGOOD

COMP

200nF

L1 = 0.82µH

×2

180µF

×2

20V

BST

CSL

PGND

CLKOUT

CLKSET

0.47µF

PV TRK

ADP1828

1.8kΩ

= 10V TO 18V

OUTPUT

1.8V, 20A

1µF

20kΩ

5.6nF

PGNDAGND

33pF

20kΩ

7.5kΩ

10kΩ

OUT1

47µF

X5R

6.3V

OUT2

1000µF

×2

680pF

100kΩ

1µF

GND

AGND

D1: BAT54

M1: INFINEON, BSC080N03LS

M2: INFINEON, 2 × BSC030N03LS

= 300kHz

: SANYO, OSCON 20SP180M

OUT2

: SANYO, POSCAP 2R5TPD1000M5

L1: WURTH ELEKTRONIC, 0.82µH, 744355182

06865-001

Figure 1. Typical Application Circuit with 20 A Output

Summary of content (36 pages)

PAGE 1
Synchronous Buck PWM, Step-Down, DC-to-DC Controller ADP1828 to regulate an output voltage as low as 0.6 V to 85% of the input voltage and is sized to handle large MOSFETs for point-of-load regulators. The ADP1828 is ideal for a wide range of high power applications, such as DSP and processor core I/O power, and general-purpose power in telecommunications, medical imaging, PC, gaming, and industrial applications.
PAGE 2
ADP1828 TABLE OF CONTENTS Features .............................................................................................. 1 Shutdown Control...................................................................... 18 Applications....................................................................................... 1 Tracking ....................................................................................... 18 General Description ................................................................
PAGE 3
ADP1828 SPECIFICATIONS IN = 12 V, PV = VEN = VTRK = 5 V, SYNC = GND, unless otherwise specified. All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). TJ = −40°C to +125°C, unless otherwise specified. Typical values are at TA = 25°C. Table 1.
PAGE 4
ADP1828 Parameter OSCILLATOR Oscillator Frequency SYNC Synchronization Range SYNC Input Pulse Width SYNC Pin Capacitance CURRENT SENSE CSL Threshold Voltage CSL Output Current Current Sense Blanking Period GATE DRIVERS DH Rise Time DH Fall Time DL Rise Time DL Fall Time DH or DL Driver RON, Sourcing Current 3, 4 DH or DL Driver RON, Sinking Current3, 4 DH or DL Driver RON, Sourcing Current DH or DL Driver RON, Sinking Current DH to DL, DL to DH Dead Time CLOCK OUT CLOCKOUT Pulse Width CLKOUT Rise or Fall T
PAGE 5
ADP1828 Parameter POWER GOOD FB Overvoltage Threshold FB Overvoltage Hysteresis FB Undervoltage Threshold FB Undervoltage Hysteresis PGOOD Propagation Delay PGOOD Off Leakage Current PGOOD Output Low Voltage Conditions Min Typ Max Unit VFB rising 700 810 VFB falling 500 750 50 550 50 8 mV mV mV mV μs μA mV VPGOOD = 5.5 V IPGOOD = 10 mA 150 1 585 1 500 Connect IN to VREG when IN < 5.5 V. For applications with IN < 5.5V and IN not connected to VREG, keep in mind that VREG = VIN – dropout.
PAGE 6
ADP1828 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter IN EN PV, SYNC, FREQ, COMP, SS, FB, PGOOD, CLKSET, CLKOUT, VREG, TRK BST-to-GND, SW-to-GND BST-to-SW BST-to-GND, SW-to-GND, 50 ns transients SW-to-GND, 30 ns negative transients CSL-to-GND DH-to-GND DL-to-PGND PGND-to-GND θJA, 20-Lead QSOP on a Multilayer PCB (Natural Convection)1 θJA, 20-Lead LFCSP on a Multilayer PCB (Natural Convection)1 Operating Junction Temperature2 Storage Temperature Maximum Soldering Lead Temperature Rating −0.3 V to +20.5 V −0.
PAGE 7
ADP1828 SIMPLIFIED BLOCK DIAGRAM IN ADP1828 LINEAR REG VREG 0.6V 0.75V REF 0.8V 0.55V THERMAL SHUTDOWN UVLO IN EN 100kΩ LOGIC BST CLKOUT CLKSET CLKOUT DRIVER FAULT DH S Q SW PWM FREQ CLK OSCILLATOR R SYNC PWM COMPARATOR RAMP Q PV DL VREG ILIM PGND 50µA COMP FB TRK CSL 0.75V ERROR AMPLIFIER 0.6V SS 90kΩ PGOOD 0.8V 0.55V 6kΩ FAULT 06865-003 GND Figure 2. Simplified Block Diagram Rev.
PAGE 8
ADP1828 20 19 18 17 16 SYNC FREQ CLKOUT CLKSET BST PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS CLKOUT 19 CLKSET EN 3 18 BST IN 4 17 DH VREG 5 16 SW GND 6 15 CSL COMP 7 14 PGND FB 8 13 DL TRK 9 12 PV SS 10 11 PGOOD ADP1828 TOP VIEW (Not to Scale) EN IN VREG GND COMP 1 2 3 4 5 (Not to Scale) ADP1828 TOP VIEW 15 14 13 12 11 DH SW CSL PGND DL NOTES 1. CONNECT THE BOTTOM EXPOSED PAD OF THE LFCSP PACKAGE TO SYSTEM AGND PLANE. Figure 3.
PAGE 9
ADP1828 QSOP Pin No. 19 LSCSP Pin No. 17 Mnemonic CLKSET 20 18 CLKOUT N/A 1 EPAD EPAD 1 Description Clock Set Input. Setting CLKSET to Logic high (connect CLKSET to VREG) sets the CLKOUT to 2× the internal oscillator frequency and is in phase with the oscillator. Setting CLKSET to Logic low sets the CLKOUT to 1× the oscillator frequency and 180° out of phase. Clock Output. The CLKOUT frequency, fCLKOUT, is either 1× or 2× the oscillator frequency.
PAGE 10
ADP1828 TYPICAL PERFORMANCE CHARACTERISTICS 95 90 300kHz 90 600kHz 85 VIN = 12V VOUT = 1.8V TA = 25°C 70 EFFICIENCY (%) EFFICIENCY (%) 80 60 50 fSW = 600kHz VIN = 12V VOUT = 3.3V TA = 25°C 80 75 70 65 60 40 2 4 6 8 10 12 LOAD (A) 14 16 18 20 50 0 2 3 4 5 LOAD (A) Figure 8. Efficiency vs. Load Current of Figure 55 Figure 5. Efficiency vs. Load Current of Figure 1 95 95 90 90 85 VIN = 12V VIN = 3.3V VIN = 5.
PAGE 11
ADP1828 5.000 3.0 VIN = 5.5V TA = 25°C 4.995 TA = 25°C 600kHz 2.5 300kHz 4.985 2.0 4.980 ∆fOSC (%) VREG OUTPUT (V) 4.990 4.975 4.970 1.5 1.0 4.965 4.960 0.5 0 20 40 60 VREG LOAD CURRENT (mA) 80 100 0 06865-010 4.950 3 Figure 11. VREG vs. Load Current 5 7 9 11 VIN (V) 13 15 06865-013 4.955 17 Figure 14. Δ fOSC vs. VIN, Referenced at VIN = 3 V 5.000 4.995 VIN = 7V T VIN = 5.5V LOAD = 5A 4.990 VREG (V) SW NO LOAD 4.985 4.980 1 4.975 10mA LOAD 4.970 4.
PAGE 12
ADP1828 2.0 T VIN = 3V TO 18V fOSC = 300kHz OR 600kHz REFERENCE POINT IS AT 25°C 1.5 VOUT (AC-COUPLED) 1 ∆fOSC (kHz) 1.0 0.5 STEP LOAD (5A TO 20A) 0 –0.5 –1.0 –25 0 25 50 75 TEMPERATURE (°C) 100 125 150 Figure 17. Δ fOSC vs. Temperature 4 06865-016 –2.0 –50 CH1 100mV M 200µs BW A CH4 8.20A CH4 5.00A Ω 06865-019 –1.5 Figure 20.
PAGE 13
ADP1828 T T VIN = 5V TO 9V TO 5V VIN 1 SS 2 VOUT 3 SW VOUT (AC-COUPLED) 1 M 4.00ms BW A CH1 6.08V 06865-022 CH1 2.00V CH3 50.0mV CH1 5.00V CH3 1.00V BW CH2 500mV CH4 5.00V BW M 2.00ms A CH1 4.10V 06865-025 4 3 Figure 26. Power-On Response, EN Tied to VIN Figure 23. Line Transient Response of Figure 1, No Load T SHORT CIRCUIT APPLIED SHORT CIRCUIT REMOVED 1 TRK SS 2 FB VOUT VIN = 5.5V 3 INPUT CURRENT 4 CH2 500mV CH4 5.00A Ω BW M 20.0ms A CH3 1.
PAGE 14
ADP1828 T T DH 1 DH 2 FB DL 3 SS VIN = 0V TO 3V 2 CLKOUT VREG 4 4.80V 4 CH1 5.00V CH3 200mV Figure 29. CLKOUT, CLKSET = 0 V BW BW CH2 200mV CH4 2.00V BW M 4.00ms A CH4 1.12V 06865-032 A CH2 8.20V 06865-033 M 1.00µs 06865-029 CH3 5.00V CH2 10.0V CH4 5.00V BW Figure 32. Start into Precharged Output T T EN 1 DH 2 DH DL 3 2 DL 4 3 CH3 5.00V CH2 10.0V CH4 5.00V M 1.00µs A CH2 4.80V 06865-030 CLKOUT CH1 5.00V CH3 5.00V Figure 30.
PAGE 15
ADP1828 THEORY OF OPERATION The ADP1828 is a versatile, synchronous-rectified, fixedfrequency, pulse-width modulation (PWM), voltage mode, step-down controller capable of generating an output voltage as low as 0.6 V to 85% of the input voltage. It is ideal for a wide range of applications, such as DSP and processor core I/O supplies, general-purpose power in telecom, medical imaging, gaming, PCs, set-top boxes, and industrial controls. The ADP1828 controller operates directly from 3 V to 20 V.
PAGE 16
ADP1828 If the output voltage is precharged prior to turn-on, the ADP1828 prevents reverse inductor current, which would discharge the output capacitor. Once the voltage at SS exceeds the regulation voltage (typically 0.6 V), the reverse current is re-enabled to allow the output voltage regulation to be independent of load current.
PAGE 17
ADP1828 The PV pin provides power to the low-side drivers. It is limited to 5.5 V maximum input and should have a local decoupling capacitor to PGND. The synchronous rectifier is turned on for a minimum time of about 200 ns on every switching cycle in order to sense the current. This minimum off-time plus the nonoverlap dead time puts a limit on the maximum high-side switch duty cycle based on the selected switching frequency. Typically, this maximum duty cycle is about 90% at 300 kHz switching. At 1.
PAGE 18
ADP1828 COMPENSATION THERMAL SHUTDOWN The control loop is compensated by an external series RC network from COMP to FB and sometimes requires a series RC in parallel with the top voltage divider resistor. COMP is the output of the internal error amplifier. In most applications, the ADP1828 controller itself does not generate a significant amount of heat under normal conditions, even when driving relatively large MOSFETs.
PAGE 19
ADP1828 APPLICATION INFORMATION SELECTING THE INPUT CAPACITOR The input current to a buck converter is a pulse waveform. It is zero when the high-side switch is off and approximately equal to the load current when it is on. The input capacitor carries the input ripple current, allowing the input power source to supply only the dc current. The input capacitor needs sufficient ripple current rating to handle the input ripple as well as an ESR that is low enough to mitigate input voltage ripple.
PAGE 20
ADP1828 During a load step transient on the output, the output capacitor supplies the load until the control loop has a chance to ramp the inductor current. This initial output voltage deviation, due to a change in load, is dependent on the output capacitor characteristics. Again, usually the capacitor ESR dominates this response, and the ΔVOUT in Equation 6 can be used with the load step current value for ΔIL. SELECTING THE MOSFETS The choice of MOSFET directly affects the dc-to-dc converter performance.
PAGE 21
ADP1828 SETTING THE CURRENT LIMIT The current-limit comparator measures the voltage across the low-side MOSFET to determine the load current. The current limit is set through the current-limit resistor, RCL. The current sense pin, CSL, sources 50 μA through the external current-limit setting resistor, RCL. This creates an offset voltage of RCL multiplied by the 50 μA CSL current.
PAGE 22
ADP1828 Depending on component selection, one zero might already be generated by the ESR of the output capacitor. Calculate this zero corner frequency, fESR, as f ESR = 1 The gain of the LC filter at crossover can be linearly approximated from Figure 37 as AFILTER = ALC + A ESR ⎛f A FILTER = −40 dB × log ⎜⎜ ESR ⎝ f LC ⎞ ⎛ f ⎟ − 20 dB × log ⎜ CO ⎟ ⎜f ⎠ ⎝ ESR ⎞ ⎟ ⎟ ⎠ (19) fLC fESR fCO –40dB/dec AFILTER PHASE 0° –90° 06865-038 ΦFILTER –180° Figure 37.
PAGE 23
ADP1828 Type II Compensator Use the following guidelines for selecting between Type II and Type III compensators: G (dB) If f ESRZ f ≤ CO , use Type II compensation. 2 If f ESRZ f > CO , use Type III compensation. 2 PHASE PHASE CONTRIBUTION AT CROSSOVER OF VARIOUS ESR ZERO CORNERS –270° –1 S LO PE –1 SL O CHF fSW RZ FREQUENCY –40dB/dec CI RTOP VOUT RBOT FB EA COMP –20dB/dec INTERNAL VREF 06865-040 0dB fP fZ –180° GAIN fLC fESR1 fESR2 fESR3 fCO PE Figure 39.
PAGE 24
ADP1828 Use the larger value of CI from Equation 31 or Equation 32. Because of the finite output current drive of the error amplifier, CI needs to be less than 10 nF. If it is larger than 10 nF, choose a larger RTOP and recalculate RZ and CI until CI is less than 10 nF. Next, calculate CI, Next, choose the high frequency pole, fP1, to be ½ of fSW. Because of the finite output current drive of the error amplifier, CI needs to be less than 10 nF.
PAGE 25
ADP1828 The ADP1828 uses an adjustable soft start to limit the output voltage ramp-up period, limiting the input inrush current. The soft start is selected by setting the capacitor, CSS, from SS to GND. The ADP1828 charges CSS to 0.8 V through an internal 90 kΩ resistor. The voltage on the soft start capacitor while it is charging is VCSS t ⎛ 90 kΩ CSS ⎜ = 0.8 V 1 − e ⎜ ⎝ ⎞ ⎟ ⎟ ⎠ In most applications, a size 0805 component is sufficient.
PAGE 26
ADP1828 VOUT EN FOR BOTH ADP1828 RTOP COMP 1 RBOT VOUT_MASTER FB TRK MASTER VOLTAGE 0.6V ERROR AMPLIFIER VOUT_SLAVE RTRKT SS TRK_SLAVE 4 Figure 42. Voltage Tracking CH1 5.00V CH3 1.00V COINCIDENT TRACKING For coincident tracking, use the following equation: RTRKT = RTOP and RTRKB = RBOT where: RTOP and RBOT are the values chosen in the Compensating the Voltage Mode Buck Regulator section. RTRKB 10kΩ BW M 100ms A CH1 1.
PAGE 27
ADP1828 A more accurate solution is to provide a divider from the master voltage that sets the TRK pin voltage to be something lower than 0.6 V at regulation, for example, 0.5 V. The slave channel can be viewed as having a 0.5 V external reference supplied by the master voltage. Keep in mind that PGOOD is tripped when the TRK voltage is set to less than 0.55 V. ADP1828 OR ADP1829 2.5V VDDQ RTRKT 40.2kΩ 0.5V SS CSS 1µF EN ADP1828 FB 1.
PAGE 28
ADP1828 THERMAL CONSIDERATIONS The current required to drive the external MOSFETs comprises the vast majority of the power dissipation of the ADP1828. The on-chip LDO regulates down to 5 V, and this 5 V supplies the drivers. The full gate drive current passes through the LDO and is then dissipated in the gate drivers. The power dissipated in the gate drivers on the ADP1828 is PD = V IN f SW (Q DH + Q DL ) (52) where: VIN is the voltage applied to IN. fSW is the switching frequency.
PAGE 29
ADP1828 PCB LAYOUT GUIDELINE In any switching converter, there are some circuit paths that carry high dI/dt, which can create spikes and noise. Other circuit paths are sensitive to noise. While other circuits carry high dc current and can produce significant IR voltage drops. The key to proper PCB layout of a switching converter is to identify these critical paths and arrange the components and the copper area accordingly. When designing PCB layouts, be sure to keep high current loops small.
PAGE 30
ADP1828 To achieve an accurate output voltage, proper grounding of the AGND and PGND planes is needed. For light to medium loads, connecting the AGND plane to the PGND plane with a trace is adequate in obtaining good output accuracy (see Figure 52). If the PGND plane is large enough and under a light to medium load, the voltage drop across the PGND plane is negligible.
PAGE 31
ADP1828 APPLICATION CIRCUITS VIN = 3.3V CIN 22µF 6.3V ×3 C5 1µF D1 VREG IN C6 1µF R6 100kΩ TRK BST PV ADP1828 DH SW EN C3 3.3nF COUT1 100µF 6.3V M1B COUT2 47µF 6.3V R3 210Ω R1 10kΩ C1 1.8nF FB COMP CLKOUT SS CLKSET CSS 100nF OUTPUT 1.2V, 5A PGND PGOOD C2 68pF 3kΩ DL SYNC M1A L1 = 1.0µH R4 CSL FREQ R8 8.06kΩ C4 0.22µF R2 10kΩ AGND PGND GND AGND fSW = 600kHz CIN: CERAMIC, 22µF/6.3V/X5R/0805 COUT1: CERAMIC, 100µF/6.3V/X5R/1210 COUT2: CERAMIC, 47µF/6.
PAGE 32
ADP1828 VBIAS = 5V VIN = 2.5V TO 8V CIN 270µF 16V ×2 C5 1µF D1 VREG IN C6 1µF R6 100kΩ TRK BST PV ADP1828 DH SW EN CSL FREQ DL SYNC C2 220pF C3 4.7nF M1 L1 = 1µH OUTPUT 1.0V, 15A R4 3.3kΩ COUT1 10µF 6.3V M2 PGND PGOOD R8 4.99kΩ C4 0.47µF COUT2 820µF 2.5V ×2 FB COMP CLKOUT SS CLKSET CSS 100nF R3 210Ω R1 10kΩ C1 1.
PAGE 33
ADP1828 OUTLINE DIMENSIONS 0.345 (8.76) 0.341 (8.66) 0.337 (8.55) 20 11 1 10 0.158 (4.01) 0.154 (3.91) 0.150 (3.81) 0.244 (6.20) 0.236 (5.99) 0.228 (5.79) 0.010 (0.25) 0.004 (0.10) COPLANARITY 0.004 (0.10) 0.010 (0.25) 0.006 (0.15) 0.069 (1.75) 0.053 (1.35) 0.065 (1.65) 0.049 (1.25) 0.025 (0.64) BSC SEATING PLANE 8° 0° 0.012 (0.30) 0.008 (0.20) 0.020 (0.51) 0.010 (0.25) 0.050 (1.27) 0.016 (0.41) 0.041 (1.
PAGE 34
ADP1828 ORDERING GUIDE Model1 ADP1828YRQZ-R7 ADP1828ACPZ-R7 ADP1828LC-EVALZ ADP1828HC-EVALZ ADP1828-BL1-EVZ ADP1828-BL2-EVZ 1 2 3 Notes 3 3 Temperature Range2 −40°C to +85°C −40°C to +85°C Package Description 20-Lead Shrink Small Outline Package [QSOP] 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] Evaluation Board (with QSOP) with 5 A Output Evaluation Board (with QSOP) with 20 A Output Low Current Blank Evaluation Board, QSOP (0 A to 20 A) High Current Blank Evaluation Board, QSOP (20 A to 30 A) Z
PAGE 35
ADP1828 NOTES Rev.