Datasheet

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Step-Down DC-to-DC Controller

ADP1821

Rev. C

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FEATURES

Wide power-input voltage range: 1 V to 24 V

Chip supply voltage range: 3.7 V to 5.5 V

Wide output voltage range: 0.6 V to 85% of input voltage

1% accuracy, 0.6 V reference voltage

All N-channel MOSFET design for low cost

Fixed-frequency operation 300 kHz, 600 kHz, or

synchronized operation up to 1.2 MHz

No current sense resistor required

Power-good output

Programmable soft start with reverse current protection

Soft start, thermal overload, current-limit protection

Undervoltage lockout

10 μA shutdown supply current

Small, 16-lead QSOP

APPLICATIONS

Telecommunications and networking systems

Set-top boxes

Printers

Servers

Medical imaging systems

Microprocessor and DSP core power supplies

Mobile communication base stations

GENERAL DESCRIPTION

The ADP1821 is a versatile and inexpensive, synchronous,

pulse-width-modulated (PWM), voltage-mode, step-down

controller. It drives an all N-channel power stage to regulate an

output voltage as low as 0.6 V. The ADP1821 can be configured

to provide output voltages from 0.6 V to 85% of the input

voltage and is sized to handle large MOSFETs for point-of-load

regulators.

The ADP1821 is well suited for a wide range of high power

applications, such as DSP and processor core power in telecom-

munications, medical imaging, high performance servers, and

industrial applications. It operates from a 3.7 V to 5.5 V supply

with a power input voltage ranging from 1.0 V to 24 V.

The ADP1821 operates at a pin-selectable, fixed switching

frequency of either 300 kHz or 600 kHz, minimizing external

component size and cost. For noise sensitive applications, it

can be synchronized to an external clock to achieve switching

frequencies between 300 kHz and 1.2 MHz. The ADP1821

includes soft start protection to limit the inrush current from

the input supply during startup, reverse current protection

during soft start for precharged outputs, as well as a unique

adjustable lossless current-limit scheme utilizing external

MOSFET sensing.

The ADP1821 operates over the –40°C to +125°C junction

temperature range and is available in a 16-lead QSOP.

GND

PVCC

ADP1821

SHDN

VCC

BST

CSL

PGND

FREQ

SYNC

PWGD

COMP

1µF

10Ω

2kΩ

300Ω

1kΩ

100kΩ

BIAS INPUT

M2 M3

L1 = 1µH

OUTPUT

1.8V, 20A

POWER INPUT

2.5V TO 20V

AGND

100nF

4.7kΩ

6.8nF

1.5nF

0.47µF

IN1

2.2µF

25V

IN2

2.2µF

25V

×2

OUT1

10µF

6.3V

×2

OUT2

820µF

2.5V

×2

10nF

= 300kHz

IN2

: SANYO, OSCON 20SP180M

OUT2

: SANYO, OSCON 2R5SEPC820M

L1: COILTRONICS, HC7-1R0

IN1

: MURATA, GRM31MR71E225k

M1: IRLR7807Z

M2, M3: IRFR3709Z

D1: VISHAY BAT54

3.3kΩ

5310-001

Figure 1. Typical Operating Circuit

LOAD CURRENT (A)

EFFICIENCY (%)

2 4 6 8 10 12 14

1.8V OUTPUT

3.3V OUTPUT

= 25°C

FREQUENCY = 300kHz

05310-002

Figure 2. Efficiency vs. Load Current, 5 V Input

Summary of content (24 pages)

PAGE 1
Step-Down DC-to-DC Controller ADP1821 FEATURES GENERAL DESCRIPTION Wide power-input voltage range: 1 V to 24 V Chip supply voltage range: 3.7 V to 5.5 V Wide output voltage range: 0.6 V to 85% of input voltage 1% accuracy, 0.6 V reference voltage All N-channel MOSFET design for low cost Fixed-frequency operation 300 kHz, 600 kHz, or synchronized operation up to 1.
PAGE 2
ADP1821 TABLE OF CONTENTS Features .............................................................................................. 1 Compensation............................................................................. 11 Applications....................................................................................... 1 Power-Good Indicator............................................................... 11 General Description .........................................................................
PAGE 3
ADP1821 SPECIFICATIONS VVCC = VPVCC = VSHDN = VFREQ = 5 V, SYNC = GND. All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). TJ = −40°C to +125°C, unless otherwise specified. Typical values are at TA=25°C. Table 1.
PAGE 4
ADP1821 Parameter LOGIC THRESHOLDS (SHDN, SYNC, FREQ) SHDN, SYNC, FREQ Input High Voltage SHDN, SYNC, FREQ Input Low Voltage SYNC, FREQ Input Leakage Current SHDN Pull-Down Resistance THERMAL SHUTDOWN Thermal Shutdown Threshold Thermal Shutdown Hysteresis PWGD OUTPUT FB Overvoltage Threshold FB Overvoltage Hysteresis FB Undervoltage Threshold FB Undervoltage Hysteresis PWGD Off Current PWGD Low Voltage Conditions Min VVCC = 3.7 V to 5.5 V VVCC = 3.7 V to 5.5 V SYNC = FREQ = GND 2.
PAGE 5
ADP1821 ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 2.
PAGE 6
ADP1821 BST 1 16 PVCC DH 2 15 DL SW 3 ADP1821 14 PGND SYNC 4 TOP VIEW (Not to Scale) 13 CSL FREQ 5 12 VCC SHDN 6 11 COMP PWGD 7 10 FB 8 9 SS GND 05310-004 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 4. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1 Mnemonic BST 2 DH 3 SW 4 SYNC 5 FREQ 6 SHDN 7 PWGD 8 9 GND SS 10 FB 11 COMP 12 VCC 13 CSL 14 15 PGND DL 16 PVCC Description High-Side Gate Driver Boost Capacitor Input.
PAGE 7
ADP1821 TYPICAL PERFORMANCE CHARACTERISTICS 97 0.6003 TA = 25°C FREQUENCY = 300kHz 96 0.6002 FEEDBACK VOLTAGE (V) 3.3V OUTPUT 95 EFFICIENCY (%) 94 93 1.8V OUTPUT 92 91 90 0.6001 0.6000 0.5999 0.5998 89 2 4 6 8 10 12 14 16 LOAD CURRENT (A) 0.5996 –50 30 50 70 90 110 100 700 TA = 25°C FREQUENCY = 300kHz SWITCHING FREQUENCY (kHz) 600 3.3V OUTPUT 90 EFFICIENCY (%) 10 Figure 8. FB Regulation Voltage vs. Temperature 92 88 1.
PAGE 8
ADP1821 OUTPUT VOLTAGE (1V/DIV) OUTPUT VOLTAGE (50mV/DIV) SHDN (5V/DIV) INPUT VOLTAGE (5V/DIV) 05310-011 05310-013 PWGD (5V/DIV) Figure 13. Power-On Response, Prebiased Output Figure 11. Line Transient Response, 10 V to 16 V OUTPUT VOLTAGE (1V/DIV) OUTPUT VOLTAGE (1V/DIV) SHDN (5V/DIV) LOAD CURRENT (10A/DIV) 05310-014 05310-012 PWGD (5V/DIV) Figure 12. Power-On Response Figure 14. Output Short-Circuit Response and Recovery Rev.
PAGE 9
ADP1821 THEORY OF OPERATION The ADP1821 is a versatile, economical, synchronous-rectified, fixed-frequency, PWM, voltage mode step-down controller capable of generating an output voltage as low as 0.6 V. It is ideal for a wide range of high power applications, such as DSP power and processor core power in telecommunications, medical imaging, and industrial applications. The ADP1821 controller operates from a 3.7 V to 5.5 V supply with a power input voltage ranging from 1.0 V to 24 V.
PAGE 10
ADP1821 MOSFET DRIVERS SETTING THE OUTPUT VOLTAGE The DH pin drives the high-side switch MOSFET. This is a boosted 5 V gate driver that is powered by a bootstrap capacitor circuit. This configuration allows the high-side, N-channel MOSFET gate to be driven above the input voltage, allowing full enhancement and a low voltage drop across the MOSFET. The bootstrap capacitor is connected from the SW pin to the BST pin.
PAGE 11
ADP1821 COMPENSATION THERMAL SHUTDOWN The control loop is compensated by an external series RC network from COMP to FB and sometimes requires a series RC in parallel with the top voltage divider resistor. COMP is the output of the internal error amplifier. The ADP1821 controller does not generate much heat under normal conditions, even when driving a relatively large MOSFET.
PAGE 12
ADP1821 APPLICATION INFORMATION Use the following equation to choose the inductor value: SELECTING THE INPUT CAPACITOR The input current to a buck converter is a pulsed waveform. It is zero when the high-side switch is off and approximately equal to the load current when it is on. The input capacitor carries the input ripple current, allowing the input power source to supply only the dc current.
PAGE 13
ADP1821 In the case of output capacitors where the impedance of the ESR and ESL are small at the switching frequency, for instance, where the output capacitor is a bank of parallel MLCC capacitors, the capacitive impedance dominates and the ripple equation reduces to ΔVOUT ≅ ΔI L (7) 8 COUT f SW Make sure that the ripple current rating of the output capacitors is greater than the maximum inductor ripple current.
PAGE 14
ADP1821 VIN SETTING THE CURRENT LIMIT ADP1821 The current-limit comparator measures the voltage across the low-side MOSFET to determine the load current. Because the CSL current and the MOSFET RDSON vary over process and temperature, the minimum current limit should be set to ensure that the system can handle the maximum desired load current.
PAGE 15
ADP1821 LC FILTER BODE PLOT For initial practical designs, a good choice for the crossover frequency is 1/10 of the switching frequency; first calculate 0dB f = SW 10 1 2π LC Depending on component selection, one zero might already be generated by the ESR of the output capacitor. Calculate this zero corner frequency, fESR, as 1 2π RESRCOUT –40dB/dec –20dB/dec AFILTER (21) PHASE 0° –90° ΦFILTER –180° Figure 16.
PAGE 16
ADP1821 Two common compensation schemes are used, which are sometimes referred to as Type II or Type III compensation, depending on whether the compensation design includes two or three poles. (Dominant pole compensations, or single pole compensation, is referred to as Type I compensation, but it is not very useful for dealing successfully with switching regulators.
PAGE 17
ADP1821 Solving for CI in Equation 33 yields CI = Next calculate CI 1 CI = (35) πRZ f LC Use the larger value of CI from Equation 34 or Equation 35. Because of the finite output current drive of the error amplifier, CI needs to be less than 10 nF. If it is larger than 10 nF, choose a larger RTOP and recalculate RZ and CI until CI is less than 10 nF.
PAGE 18
ADP1821 The soft start period, tSS, is achieved when VCSS = 0.6 V or SETTING THE SOFT START PERIOD The ADP1821 uses an adjustable soft start to limit the output voltage ramp-up period, limiting the input inrush current. The soft start is set by selecting the capacitor, CSS, from SS to GND. The ADP1821 charges CSS to 0.8 V through an internal 100 kΩ resistor. The voltage on CSS while it is charging is VCSS t ⎛ RCSS ⎜ = 0.8 V 1 − e ⎜ ⎝ ⎞ ⎟ ⎟ ⎠ t SS ⎞ ⎛ 0.6 V = 0.
PAGE 19
ADP1821 PCB LAYOUT GUIDELINE In any switching converter, there are some circuit paths that carry high dI/dt, which can create spikes and noise. Other circuit paths are sensitive to noise and still others carry high dc current and can produce significant IR voltage drops. The key to proper PCB layout of a switching converter is to identify these critical paths and arrange the components and copper area accordingly. When designing PCB layouts, be sure to keep high current loops small.
PAGE 20
ADP1821 05310-020 VIA TO 2 LAYER SOME TRACES ARE OMITTED FOR CLARITY Figure 20. Top Layer Layout Example of Circuit (See Figure 23) Figure 21. Bottom Layer Layout Example of Circuit (See Figure 23) RECOMMENDED COMPONENT MANUFACTURERS Table 4. Vendor AVX Corporation Central Semiconductor Corp. Coilcraft®, Inc. Diodes, Inc. International Rectifier Murata Manufacturing Co., Ltd. ON Semiconductor® Rubycon Corporation Sanyo Sumida Corporation Taiyo Yuden, Inc. Toko America, Inc. United Chemi-Con, Inc.
PAGE 21
ADP1821 APPLICATION CIRCUITS The ADP1821 controller can be configured to regulate an output with a load of more than 20 A if the power components, such as the inductor, MOSFETs, and the bulk capacitors are chosen carefully to meet the power requirement. The maximum load and power dissipation are limited by the power-train components. Figure 1 shows a typical application circuit that can drive an output load of 20 A. Note that two low-side MOSFETs are needed to deliver the 20 A load.
PAGE 22
ADP1821 The ADP1821 can also be configured to run with an input voltage higher than 5.5 V. Figure 23 shows a typical application circuit that operates from a 12 V input. An external LDO is built, with an NPN, a 5.6 V Zener diode, and a resistor to step down the R7 10Ω C6 1µF D1 VCC R5 1.2kΩ PVCC BST DH SW SYNC PWGD CSL C4 0.22µF M2 PGND SS + CIN2 180µF 20V M1 L1 = 2.2µH R4 3.3kΩ DL COMP INPUT 12V CIN1 10µF 16V ADP1821 FREQ R8 82kΩ D2 C5 1µF SHDN R6 100kΩ Q1 OUTPUT 1.
PAGE 23
ADP1821 OUTLINE DIMENSIONS 0.197 0.193 0.189 9 16 0.158 0.154 0.150 1 8 0.244 0.236 0.228 PIN 1 0.069 0.053 0.065 0.049 0.010 0.025 0.004 BSC COPLANARITY 0.004 0.012 0.008 SEATING PLANE 0.010 0.006 8° 0° 0.050 0.016 COMPLIANT TO JEDEC STANDARDS MO-137-AB Figure 24.