Datasheet

ADP1754/ADP1755 Data Sheet
Rev. F | Page 6 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
1VIN
2VIN
3VIN
4EN
11 VOUT
12 VOUT
10 VOUT
9 SENSE
5
PG
6
GND
7
SS
8
NC
15
VIN
16
VIN
14
VOUT
13
VOUT
TOP VIEW
(Not to Scale)
ADP1754
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PAD ON THE BOTTOM OF THE LFCSP ENHANCES
THERMAL PERFORMANCE AND IS ELECTRICALLY CONNECTED TO GND
INSIDE THE PACKAGE. IT IS RECOMMENDED THAT THE EXPOSED PAD
BE CONNECTED TO THE GROUND PLANE ON THE BOARD.
07722-003
PIN 1
INDICATOR
1
VIN
2
VIN
3
VIN
4
EN
11
VOUT
12
VOUT
10
VOUT
9
ADJ
5PG
6GND
7SS
8NC
15
VIN
16
VIN
14
VOUT
13
VOUT
TOP VIEW
(Not to Scale)
ADP1755
NOTES
1.
NC = NO CONNECT.
2.
THE EXPOSED PAD ON THE BOTTOM OF THE LFCSP ENHANCES
THERMAL PERFORMANCE AND IS ELECTRICALLY CONNECTED TO GND
INSIDE THE PACKAGE. IT IS RECOMMENDED THAT THE EXPOSED PAD
BE CONNECTED TO THE GROUND PLANE ON THE BOARD.
07722-004
Figure 3. ADP1754 Pin Configuration Figure 4. ADP1755 Pin Configuration
Table 5. Pin Function Descriptions
ADP1754
Pin No.
ADP1755
Pin No.
Mnemonic Description
1, 2, 3, 15,
16
1, 2, 3, 15,
16
VIN Regulator Input Supply. Bypass VIN to GND with a 4.7 µF or greater capacitor. Note that all five
VIN pins must be connected to the source.
4 4 EN Enable Input. Drive EN high to turn on the regulator; drive it low to turn off the regulator. For
automatic startup, connect EN to VIN.
5 5 PG Power Good. This open-drain output requires an external pull-up resistor to VIN. If the part is in
shutdown mode, current-limit mode, thermal shutdown, or if it falls below 90% of the nominal
output voltage, PG immediately transitions low.
6
6
GND
Ground.
7 7 SS Soft Start. A capacitor connected to this pin determines the soft start time.
8 8 NC Not Connected. No internal connection.
9 N/A SENSE Sense. This pin measures the actual output voltage at the load and feeds it to the error
amplifier. Connect SENSE as close as possible to the load to minimize the effect of IR drop
between the regulator output and the load.
N/A 9 ADJ Adjust. A resistor divider from VOUT to ADJ sets the output voltage.
10, 11, 12,
13, 14
10, 11, 12,
13, 14
VOUT Regulated Output Voltage. Bypass VOUT to GND with a 4.7 µF or greater capacitor. Note that all
five VOUT pins must be connected to the load.
17 (EPAD) 17 (EPAD) Exposed
paddle
(EPAD)
The exposed pad on the bottom of the LFCSP package enhances thermal performance and is
electrically connected to GND inside the package. It is recommended that the exposed pad be
connected to the ground plane on the board.