Datasheet

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0.8 A, Low V

, Low Dropout

Linear Regulator

Data Sheet

ADP1752/ADP1753

Rev. F Document Feedback

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FEATURES

Maximum output current: 0.8 A

Input voltage range: 1.6 V to 3.6 V

Low shutdown current: <2 µA

Very low dropout voltage: 70 mV at 0.8 A load

Initial accuracy: ±1%

Accuracy over line, load, and temperature: ±2%

7 fixed output voltage options with soft start

0.75 V to 2.5 V (ADP1752)

Adjustable output voltage option with soft start

0.75 V to 3.3 V (ADP1753)

High PSRR

65 dB at 1 kHz

65 dB at 10 kHz

54 dB at 100 kHz

23 μV rms at 0.75 V output

Stable with small 4.7 µF ceramic output capacitor

Excellent load and line transient response

Current-limit and thermal overload protection

Power-good indicator

Logic-controlled enable

Reverse current protection

APPLICATIONS

Server computers

Memory components

Telecommunications equipment

Network equipment

DSP/FPGA/microprocessor supplies

Instrumentation equipment/data acquisition systems

TYPICAL APPLICATION CIRCUITS

TOP VIEW

(Not to Scale)

ADP1752

VIN

100kΩ

4.7µF 4.7µF

= 1.8V

OUT

= 1.5V

VIN

VOUT

SENSE

GND

VIN

VOUT

10nF

07718-001

Figure 1. ADP1752 with Fixed Output Voltage, 1.5 V

TOP VIEW

(Not to Scale)

ADP1753

VIN

100kΩ

4.7µF

= 1.8V V

OUT

= 0.5V(1 + R1/R2)

VIN

VOUT

ADJ

GND

VIN

VOUT

10nF

07718-002

Figure 2. ADP1753 with Adjustable Output Voltage, 0.75 V to 3.3 V

GENERAL DESCRIPTION

The ADP1752/ADP1753 are low dropout (LDO) CMOS linear

regulators that operate from 1.6 V to 3.6 V and provide up to

800 mA of output current. These low V

OUT

LDOs are ideal

for regulation of nanometer FPGA geometries operating from

2.5 V down to 1.8 V I/O rails, and for powering core voltages

down to 0.75 V. Using an advanced proprietary architecture,

they provide high power supply rejection ratio (PSRR) and low

noise, and achieve excellent line and load transient response

with only a small 4.7 µF ceramic output capacitor.

The ADP1752 is available in seven fixed output voltage options.

The ADP1753 is the adjustable version, which allows output

voltages that range from 0.75 V to 3.3 V via an external divider.

The ADP1752/ADP1753 allow an external soft start capacitor

to be connected to program the startup. A digital power-good

output allows power system monitors to check the health of the

output voltage.

The ADP1752/ADP1753 are available in a 16-lead, 4 mm × 4 mm

LFCSP, making them not only very compact solutions, but also

providing excellent thermal performance for applications that

require up to 800 mA of output current in a small, low profile

footprint.

Summary of content (20 pages)

PAGE 1
0.8 A, Low VIN, Low Dropout Linear Regulator ADP1752/ADP1753 Data Sheet FEATURES TYPICAL APPLICATION CIRCUITS VIN = 1.8V VOUT = 1.5V 4.7µF 4.7µF 1 VIN 100kΩ VOUT 12 ADP1752 2 VIN TOP VIEW (Not to Scale) 3 VIN VOUT 11 VOUT 10 PG 4 EN SENSE 9 PG 5 GND 6 SS 7 NC 8 10nF Figure 1. ADP1752 with Fixed Output Voltage, 1.5 V VOUT = 0.5V(1 + R1/R2) VIN = 1.8V 4.7µF 4.
PAGE 2
ADP1752/ADP1753 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Soft Start Function (ADP1752/ADP1753) ............................. 11 Applications ....................................................................................... 1 Adjustable Output Voltage (ADP1753) ................................... 12 Typical Application Circuits............................................................
PAGE 3
Data Sheet ADP1752/ADP1753 SPECIFICATIONS VIN = (VOUT + 0.4 V) or 1.6 V (whichever is greater), IOUT = 10 mA, CIN = COUT = 4.7 µF, TA = 25°C, unless otherwise noted. Table 1.
PAGE 4
ADP1752/ADP1753 Data Sheet Parameter OUTPUT NOISE Symbol OUTNOISE POWER SUPPLY REJECTION RATIO PSRR Test Conditions/Comments 10 Hz to 100 kHz, VOUT = 0.75 V 10 Hz to 100 kHz, VOUT = 2.5 V VIN = VOUT + 1 V, IOUT = 10 mA 1 kHz, VOUT = 0.75 V 1 kHz, VOUT = 2.5 V 10 kHz, VOUT = 0.75 V 10 kHz, VOUT = 2.5 V 100 kHz, VOUT = 0.75 V 100 kHz, VOUT = 2.5 V Min Typ 23 65 Max 65 56 65 56 54 51 Unit µV rms µV rms dB dB dB dB dB dB Minimum output load current is 500 μA.
PAGE 5
Data Sheet ADP1752/ADP1753 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter VIN to GND VOUT to GND EN to GND SS to GND PG to GND SENSE/ADJ to GND Storage Temperature Range Junction Temperature Range Junction Temperature Soldering Conditions Rating −0.3 V to +4.0 V −0.3 V to VIN −0.3 V to VIN −0.3 V to VIN −0.3 V to +4.0 V −0.3 V to VIN −65°C to +150°C −40°C to +125°C 150°C JEDEC J-STD-020 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.
PAGE 6
ADP1752/ADP1753 Data Sheet ADP1752 11 VOUT VIN 2 ADP1753 11 VOUT TOP VIEW (Not to Scale) 10 VOUT VIN 3 10 VOUT 9 SENSE EN 4 TOP VIEW (Not to Scale) NOTES 1. NC = NO CONNECT. 2. THE EXPOSED PAD ON THE BOTTOM OF THE LFCSP ENHANCES THERMAL PERFORMANCE AND IS ELECTRICALLY CONNECTED TO GND INSIDE THE PACKAGE. IT IS RECOMMENDED THAT THE EXPOSED PAD BE CONNECTED TO THE GROUND PLANE ON THE BOARD. 07718-003 12 VOUT 9 ADJ NC 8 PG 5 NC 8 PG 5 SS 7 VIN 3 GND 6 VIN 2 NOTES 1. NC = NO CONNECT.
PAGE 7
Data Sheet ADP1752/ADP1753 TYPICAL PERFORMANCE CHARACTERISTICS VIN = 1.9 V, VOUT = 1.5 V, IOUT = 10 mA, CIN = 4.7 µF, COUT = 4.7 µF, TA = 25°C, unless otherwise noted. 1.520 1000 LOAD = 800mA 900 1.515 GROUND CURRENT (µA) LOAD = 10mA 1.505 LOAD = 100mA 1.500 LOAD = 400mA 1.495 LOAD = 800mA 1.490 LOAD = 400mA 700 600 500 LOAD = 100mA 400 300 LOAD = 10mA 200 1.485 100 –40 –5 25 85 0 07718-105 1.480 125 JUNCTION TEMPERATURE (°C) –40 –5 25 85 07718-108 OUTPUT VOLTAGE (V) 800 1.
PAGE 8
ADP1752/ADP1753 Data Sheet 100 4500 1.9V 2.0V 2.4V 2.6V 3.0V 3.6V 70 3500 60 50 40 30 3000 2500 2000 1500 1000 20 500 10 –15 10 35 60 85 TEMPERATURE (°C) 0 2.3 07718-111 0 –40 Figure 11. Shutdown Current vs. Temperature at Various Input Voltages 2.4 2.6 2.7 2.8 Figure 14. Ground Current vs. Input Voltage (in Dropout), VOUT = 2.5 V 0.08 T ILOAD 0.07 DROPOUT VOLTAGE (V) 2.5 INPUT VOLTAGE (V) 0.06 1 0.05 1mA TO 800mA LOAD STEP, 2.5A/µs, 500mA/DIV 0.04 1.6V VOUT 2 0.
PAGE 9
Data Sheet ADP1752/ADP1753 0 T VIN –10 –20 3V TO 3.5V INPUT VOLTAGE STEP, 2V/µs PSRR (dB) –30 VOUT 2 –40 –50 –60 2mV/DIV –70 –90 CH1 500mV BW CH2 2.0mV B W M10µs A CH4 800mA T 9.40% –100 10 07718-117 1 100 1k 10k 100k 1M 10M FREQUENCY (Hz) 07718-120 800mA 400mA 100mA 10mA –80 VOUT = 1.5V CIN = COUT = 4.7µF Figure 20. Power Supply Rejection Ratio vs. Frequency, VOUT = 0.75 V, VIN = 1.75 V Figure 17. Line Transient Response, Load Current = 800 mA 0 70 –10 2.
PAGE 10
ADP1752/ADP1753 0 –10 1.5V/800mA 2.5V/800mA 0.75V/800mA Data Sheet 1.5V/10mA 2.5V/10mA 0.75V/10mA –20 PSRR (dB) –30 –40 –50 –60 –70 –90 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 07718-123 –80 Figure 23. Power Supply Rejection Ratio vs. Frequency and Output Voltage Rev.
PAGE 11
Data Sheet ADP1752/ADP1753 THEORY OF OPERATION The ADP1752/ADP1753 are low dropout linear regulators that use an advanced, proprietary architecture to provide high power supply rejection ratio (PSRR) and excellent line and load transient response with only a small 4.7 µF ceramic output capacitor. Both devices operate from a 1.6 V to 3.6 V input rail and provide up to 0.8 A of output current. Supply current in shutdown mode is typically 2 µA.
PAGE 12
ADP1752/ADP1753 T Data Sheet The EN pin active/inactive thresholds are derived from the VIN voltage. Therefore, these thresholds vary with changing input voltage. Figure 29 shows typical EN active/inactive thresholds when the input voltage varies from 1.6 V to 3.6 V. EN 1 1.1 1.0 500mV/DIV CH1 2.0V BW VOUT = 1.5V CIN = COUT = 4.7µF CH2 500mV BW M40µs T 9.8% A CH1 920mV 07718-022 2 EN THRESHOLD (V) VOUT Figure 27. VOUT Ramp-Up with Internal Soft Start 0.9 EN ACTIVE 0.8 EN INACTIVE 0.7 0.
PAGE 13
Data Sheet ADP1752/ADP1753 REVERSE CURRENT PROTECTION FEATURE T VIN 1V/DIV 1 VOUT 500mV/DIV PG 1V/DIV 2 CH1 1.0V BW CH3 1.0V BW CH2 500mV BW M40.0µs A CH3 T 50.40% 900mV 07718-025 VOUT = 1.5V CIN = COUT = 4.7µF Figure 30. Typical PG Behavior vs. VOUT, VIN Rising (VOUT = 1.5 V) The ADP1752/ADP1753 have additional circuitry to protect against reverse current flow from VOUT to VIN. For a typical LDO with a PMOS pass device, there is an intrinsic body diode between VIN and VOUT.
PAGE 14
ADP1752/ADP1753 Data Sheet APPLICATIONS INFORMATION CAPACITOR SELECTION Input Bypass Capacitor Output Capacitor Connecting a 4.7 μF capacitor from the VIN pin to GND reduces the circuit sensitivity to printed circuit board (PCB) layout, especially when long input traces or high source impedance are encountered. If output capacitance greater than 4.7 μF is required, it is recommended that the input capacitor be increased to match it.
PAGE 15
Data Sheet ADP1752/ADP1753 In this example, the worst-case temperature coefficient (TEMPCO) over −40°C to +85°C is assumed to be 15% for an X5R dielectric. The tolerance of the capacitor (TOL) is assumed to be 10%, and COUT = 4.46 μF at 1.8 V, as shown in Figure 35. Substituting these values in Equation 3 yields CEFF = 4.46 μF × (1 − 0.15) × (1 − 0.1) = 3.
PAGE 16
ADP1752/ADP1753 140 JUNCTION TEMPERATURE, TJ (°C) 120 100 LOAD = 800mA 80 LOAD = 400mA 60 LOAD = 200mA 40 0.75 1.25 1.75 2.25 2.75 VIN – VOUT (V) LOAD = 800mA 100 LOAD = 400mA 80 LOAD = 200mA 60 20 0 0.25 JUNCTION TEMPERATURE, TJ (°C) LOAD = 800mA 100 LOAD = 400mA 80 LOAD = 200mA 60 40 LOAD = 100mA LOAD = 50mA LOAD = 10mA 0.75 1.25 1.75 2.25 2.75 VIN – VOUT (V) LOAD = 800mA LOAD = 200mA 80 60 JUNCTION TEMPERATURE, TJ (°C) LOAD = 200mA 80 LOAD = 100mA 40 20 LOAD = 10mA 20 1.25 1.
PAGE 17
Data Sheet ADP1752/ADP1753 (7) Figure 42 through Figure 45 show junction temperature calculations for different board temperatures, load currents, VIN to VOUT differentials, and areas of PCB copper. MAX JUNCTION TEMPERATURE 120 LOAD = 800mA 80 LOAD = 400mA 60 LOAD = 200mA 40 20 LOAD = 100mA LOAD = 50mA LOAD = 10mA 0.75 1.25 1.75 2.25 2.75 VIN – VOUT (V) 100 Figure 44. 1000 mm2 of PCB Copper, TB = 25°C, LFCSP LOAD = 800mA 140 LOAD = 200mA 40 20 LOAD = 100mA LOAD = 50mA LOAD = 10mA 1.25 0.
PAGE 18
ADP1752/ADP1753 Data Sheet PCB LAYOUT CONSIDERATIONS Heat dissipation from the package can be improved by increasing the amount of copper attached to the pins of the ADP1752/ ADP1753. However, as shown in Table 6, a point of diminishing returns is eventually reached, beyond which an increase in the copper size does not yield significant heat dissipation benefits. Here are a few general tips when designing PCBs: • • • Place the input capacitor as close as possible to the VIN and GND pins.
PAGE 19
Data Sheet ADP1752/ADP1753 OUTLINE DIMENSIONS 4.10 4.00 SQ 3.90 0.60 MAX 1.95 REF 0.60 MAX 13 PIN 1 INDICATOR 16 1 12 PIN 1 INDICATOR 3.75 BSC SQ 0.65 BSC 2.25 2.10 SQ 1.95 EXPOSED PAD 9 1.00 0.85 0.80 SEATING PLANE 12° MAX 0.80 MAX 0.65 TYP 0.35 0.30 0.25 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 4 8 5 BOTTOM VIEW 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 02-26-2013-B TOP VIEW 0.75 0.