Datasheet

Data Sheet ADP1740/ADP1741
Rev. F | Page 13 of 20
2
2
CH1 1.0V
B
W
CH3 1.0V
B
W
CH2 500mV
B
W
M40.0µs A CH3 900mV
1
T 50.40%
T
07081-029
V
IN
1V/DIV
V
OUT
500mV/DIV
PG
1V/DIV
V
OUT
= 1.5V
C
IN
= C
OUT
= 4.7µF
Figure 30. Typical PG Behavior vs. V
OUT
, V
IN
Rising (V
OUT
= 1.5 V)
2
2
CH1 1.0V
B
W
CH3 1.0V
B
W
CH2 500mV
B
W
M40.0µs
A CH3 900mV
1
T 50.40%
T
07081-030
V
IN
1V/DIV
V
OUT
500mV/DIV
PG
1V/DIV
V
OUT
= 1.5V
C
IN
= C
OUT
= 4.7µF
Figure 31. Typical PG Behavior vs. V
OUT
, V
IN
Falling (V
OUT
= 1.5 V)
REVERSE CURRENT PROTECTION FEATURE
The ADP1740/ADP1741 have additional circuitry to protect
against reverse current flow from VOUT to VIN. For a typical
LDO with a PMOS pass device, there is an intrinsic body diode
between VIN and VOUT. When V
IN
is greater than V
OUT
, this
diode is reverse-biased. If V
OUT
is greater than V
IN
, the intrinsic
diode becomes forward-biased and conducts current from
VOUT to VIN, potentially causing destructive power dissipation.
The reverse current protection circuitry detects when V
OUT
is
greater than V
IN
and reverses the direction of the intrinsic diode
connection, reverse-biasing the diode. The gate of the PMOS
pass device is also connected to VOUT, keeping the device off.
Figure 32 shows a plot of the reverse current vs. the V
OUT
to V
IN
differential.
4000
3500
3000
2500
2000
1500
1000
500
0
0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6
REVERSE CURRENT (µA)
V
OUT
– V
IN
(V)
07081-132
Figure 32. Reverse Current vs. V
OUT
− V
IN