Datasheet

ADP1660 Data Sheet
Rev. 0 | Page 6 of 28
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Rating
VIN, SDA, SCL, EN, GPIO, STROBE,
LED1, LED2, SW, VOUT to PGND
−0.3 V to +6 V
PGND to SGND −0.3 V to +0.3 V
Ambient Temperature Range (T
A
) −40°C to +85°C
Junction Temperature Range (T
J
) −40°C to +125°C
Storage Temperature JEDEC J-STD-020
ESD
Human Body Model
±1000 V
Charged Device Model ±500 V
Machine Model ±150 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL DATA
The ADP1660 may be damaged if the junction temperature
(T
J
) limits are exceeded. Monitoring ambient temperature (T
A
)
does not guarantee that T
J
is within the specified temperature
limits. In applications with high power dissipation and poor PCB
thermal resistance, the maximum T
A
may need to be derated.
In applications with moderate power dissipation and low PCB
thermal resistance, the maximum T
A
can exceed the maximum
limit as long as T
J
is within the specification limits.
The junction temperature (T
J
) of the device is dependent on
the ambient temperature (T
A
), the power dissipation (P
D
) of the
device, and the junction-to-ambient thermal resistance (θ
JA
) of
the package. Maximum T
J
is calculated from T
A
and P
D
using
the following formula:
T
J
= T
A
+ (P
D
× θ
JA
)
THERMAL RESISTANCE
The junction-to-ambient thermal resistance (θ
JA
) of the package
is based on modeling and calculation using a 4-layer board. θ
JA
is highly dependent on the application and board layout. In
applications where high maximum power dissipation exists,
close attention to thermal board design is required.
The value of θ
JA
may vary, depending on PCB material, layout,
and environmental conditions. The specified value of θ
JA
is based
on a 4-layer, 4 inch × 3 inch, 2½ oz copper board, per JEDEC
standards. For more information, see the AN-617 Application
Note, Wafer Level Chip Scale Package.
In Table 5, θ
JA
is specified for a device mounted on a JEDEC
2S2P PCB.
Table 5. Thermal Resistance
Package Type θ
JA
Unit
12-Ball WLCSP
75
°C/W
ESD CAUTION