Datasheet

ADP1650
Rev. C | Page 28 of 32
PCB LAYOUT
Poor layout can affect performance, causing electromagnetic
interference (EMI) and electromagnetic compatibility (EMC)
problems, ground bounce, and power losses. Poor layout can
also affect regulation and stability. Figure 45 shows optimized
layouts implemented using the following guidelines:
• Place the inductor, input capacitor, and output capacitor
close to the IC using short tracks. These components carry
high switching frequencies and large currents.
• Route the trace from the inductor to the SW pin with as
wide a trace as possible. The easiest path is through the
center of the output capacitor.
• Route the LED_OUT path away from the inductor and SW
node to minimize noise and magnetic interference.
• Maximize the size of ground metal on the component side
to help with thermal dissipation.
• Use a ground plane with two to three vias connecting to the
component side ground near the output capacitor to
reduce noise interference on sensitive circuit nodes.
• With the LFCSP package, six to eight thermal vias connect
the ground paddle to the main PCB ground plane.
• Analog Devices applications engineers can be contacted
through the Analog Devices sales team to discuss different
layouts based on system design constraints.
0
8837-023
DIGITAL
INPUT/
OUTPUT
Li-ION +
Li-ION +
PGND
C
1
L1
INDUCTOR
LED
ANODE
C2
AREA = 16.4mm
2
Figure 45. Layout of the ADP1650 Driving a High Power White LED (WLCSP)
08837-024
C1
A
DP1650
Li-ION +
L1
INDUCTOR
PGND
GND
PGND
VOUT
SDA
SCL
GPIO2
G
PI
O
1
STROBE
EN
SW
VOUT
LED_OUT
VIN
C2
Figure 46. Example Layout of the ADP1650 Driving a High Power White LED (LFCSP)