Datasheet
ADP1650
Rev. C | Page 20 of 32
I
2
C REGISTER MAP
The lowest bit number (0) represents the least significant bit, and the highest bit number (7) represents the most significant bit.
Table 9. Design Information Register (Register 0x00)
Bit R/W Reset State
[7:0] R 00100010
Table 10. VREF and Timer Register (Register 0x02)
Bit Name Bit R/W Description
IO2_CFG [7:6] R/W
GPIO2 configuration
00 = high impedance (default)
01 = indicator LED
10 = TxMASK2 operation mode
11 = analog input (to ADC)
IO1_CFG [5:4] R/W
GPIO1 configuration
00 = high impedance (default)
01 = torch
10 = TxMASK1 operation mode
11 = reserved
FL_TIM [3:0] R/W Flash timer value setting
0000 = 100 ms
0001 = 200 ms
0010 = 300 ms
0011 = 400 ms
0100 = 500 ms
0101 = 600 ms
0110 = 700 ms
0111 = 800 ms
1000 = 900 ms
1001 = 1000 ms
1010 = 1100 ms
1011 = 1200 ms
1100 = 1300 ms
1101 = 1400 ms
1110 = 1500 ms
1111 = 1600 ms (default)