Datasheet

EVAL-ADP1621
Rev. 0 | Page 9 of 12
EVALUATION BOARD SCHEMATIC AND ARTWORK
06358-001
SDSN
GND
COMP
FB
FREQ
IN
CS
PIN
GATE
PGND
U1
ADP1621
R5
36kΩ
1%
JP1
12
R4
15kΩ
1%
C12
3.3nF
C13
390pF
1
2
3
4
5
TP7
2
1
J3
R14
100kΩ
R13
100kΩ
TP8
R2
5.6kΩ
1%
R1
17.4kΩ
1%
R3
OPEN
C14
OPEN
V
OUT
10
9
8
7
6
C9
0.1µF
C10
1µF
R8
0Ω
R7
2Ω
TP6
RA9
OPEN
RB9
0Ω
V
IN
V
OUT
C11
OPEN
R6
150Ω, 1%
RA10
0Ω
RB10
OPEN
CSL1
CSL2
GATE
Q1
OPEN
1
1
1
1
1
1
1. IF A CURRENT SENSE RESISTOR IS NOT USED,
THEN REMOVE RB10 AND ASSEMBLE RA10.
OTHERWISE REMOVE RA10 AND ASSEMBLE RB10.
2. IN BOOTSTRAPPING MODE, REMOVE RA9
AND ASSEMBLE RB9. OTHERWISE REMOVE RB9
AND ASSEMBLE RA9.
3. FOR HIGH INPUT VOLTAGES, REMOVE R8 AND
ASSEMBLE Q1. OTHERWISE REMOVE Q1 AND
ASSEMBLE R8.
4. FOR THE OUTPUT FILTER, IF CERAMIC CAPACITOR
FILTER IS USED, ASSEMBLE C4 TO C8.
IF ELECTROLYTIC CAPACITOR FILTER IS USED,
ASSEMBLE CE1 TO CE3.
NOTES
1. R13 AND R14 ARE USED FOR PROBING OF THE FB AND COMP NODES, RESPECTIVELY.
2. R7 AND R12 ARE OPTIONAL. R7 (2Ω) IS USED FOR FILTERING OUT SOME OF THE UNWANTED NOISE AT THE IN PIN.
R12 (2Ω) IS USED FOR REDUCING THE RINGING AND NOISE AT THE GATE PIN AND THE DRAIN OF THE MOFSET.
M1
IRF7470
R11
0Ω, 1%
R12
2Ω
TP4*
GATE
CSL2
CSL1
TP5*
L1
2.5µH
12
D1
VISHAY SSA33L
12
D4 D3 D2 D1
GS3S2S1
5678
4321
1
1
1
1
C3
47µF
6.3V
X5R
1206
C2
OPEN
C1
OPEN
+
CE5
OPEN
+
CE4
OPEN
1
2
1
2
C6
OPEN
C5
10µF
16V
X7R
1210
C4
10µF
16V
X7R
1210
C8
10µF
16V
X7R
1210
C7
10µF
16V
X7R
1210
+
CE2
OPEN
+
CE1
OPEN
1
2
1
2
+
CE3
OPEN
1
2
TP3*
1
1
V
OUT
J2
1
2
J1
2
1
V
IN
T
P1*
1
1
TP2*
1
1
A
DP1621 BOOST DEMO BOARD
V
IN
= 3.3V, V
O
= 5V @ 2A
*TP1 TO TP5 ARE TEST POINTS.
Figure 13. ADP1621 Evaluation Board Schematic