Datasheet

EVAL-ADP1621
Rev. 0 | Page 8 of 12
PCB LAYOUT GUIDELINE
Layout is important for all switching regulators, but is
particularly important for regulators with high switching
frequencies. To achieve high efficiency, good regulation, and
stability, a well-designed printed circuit board layout is
required. A sample 2-layer PCB layout for the standard boost
converter circuit is shown in Figure 12.
Follow these guidelines when designing printed circuit boards:
• Keep the low ESR input capacitor, C
IN
, close to IN, PIN
and PGND.
• Keep the high current path from C
IN
through Inductor L1
and MOSFET M1 to PGND as short as possible.
• Keep the high current path from C
IN
through Inductor L1,
Diode D1, and Output Capacitor C
OUT
as short as possible.
• Keep high current traces as short and wide as possible to
minimize parasitic series inductance, which causes spiking
and electromagnetic interference (EMI).
• Place the feedback resistors as close to FB as possible to
prevent high frequency switching-noise injection.
• Place the top of the upper feedback resistor, R1, as
close as possible to the top of C
OUT
for optimum output
voltage sensing.
• If a current-sense resistor is connected between the source
of the MOSFET and PGND, ensure that the capacitance
from CS to PGND is minimized.
• Place the compensation components as close as possible
to COMP.
• To minimize switching noise, the drain of the power
MOSFET should be placed very close to the inductor, and
the source of the MOSFET (or the bottom side of the sense
resistor) should be connected directly to the power GND
plane. Use wide copper traces on the drain and on the
source of the MOSFET to minimize parasitic inductance
and resistance. Parasitic inductance can lead to excessive
ringing during switching transitions, and parasitic
resistance reduces the converter efficiency. Make sure that
the MOSFET selected is capable of handling total power loss
(conduction plus transition losses) in the application circuit.
• Avoid routing high impedance traces near any node
connected to the switch node (the MOSFET drain) or near
Inductor L1 to prevent radiated switching-noise injection.
• Add an extra copper plane at the connection of the
MOSFET drain and the anode of the diode to help
dissipate the heat generated by losses in those components.
• Avoid ground loops by having one central ground node on
the PCB. If this is impractical, place the power ground with
high current levels physically closer to the PCB ground
terminal. The analog, low current-level ground should be
placed farther from the PCB ground terminal.
• Minimize the length of the PCB trace between the GATE
pin and the MOSFET gate. The parasitic inductance in this
PCB trace can give rise to excessive voltage ringing at the
drain and the output. It is recommended to add 5 Ω of
resistance for every inch of PCB trace. This helps to reduce
the overshoot and ringing at the drain and the output.
However, this added resistance increases the rise and fall
times of the MOSFET; thus, the switching loss in the
MOSFET is increased.
V
IN
VIAS TO GND PLANE
VIAS TO 2ND LAYER
REMOTE OUTPUT
SENSING
L1
GND
C1
GND
SDSN
ADP1621
C3
C2 R1 R2
C4
R
FREQ
R
COMP
R
S
C
COMP
GATE
D1
M1
V
OUT
C
OUT1
C
OUT2
C
OUT3
06358-012
Figure 12. Boost Converter Layout (2-layer PCB)
OTHER CONFIGURATIONS
The demo board can be easily modified for other input voltage
and output voltage options.
• For a nonbootstrapping configuration, assemble RA9 = 0 Ω,
and remove RB9.
• For input voltages higher than 6 V, an NPN transistor Q1
and R7 can be assembled to form an LDO that brings
down the input voltage down to 5 V to power the
ADP1621. Alternatively, RA9 can be used to bring down
the input voltage to the shunt regulation voltage, V
SHUNT
.
The drawback in using a large RA9 resistor is the higher
power dissipation in this resistor when driving a large
MOSFET or when the input voltage range is large.
• For output voltages higher than 28 V, connect the CS pin to
the current sense resistor R11. On the current demo board
version, R11 is a 0 Ω resistor. Make sure the MOSFET V
DS
is rated for at least 40 V.
• The surface-mount ceramic capacitors are used on this
demo board; other types of bulk input and output
capacitors can also be used. The board is laid out to
accommodate the surface-mount aluminum polymer and
the through-hole aluminum electrolytic capacitors.