Datasheet

ADP1612/ADP1613 Data Sheet
Rev. D | Page 24 of 28
PCB LAYOUT GUIDELINES
06772-076
Figure 76. Example Layout for ADP1612/ADP1613 Boost Application
(Top Layer)
06772-077
Figure 77. Example Layout for ADP1612/ADP1613 Boost Application
(Bottom Layer)
For high efficiency, good regulation, and stability, a well-designed
printed circuit board layout is required.
Use the following guidelines when designing printed circuit
boards (also see Figure 34 for a block diagram and Figure 3
for a pin configuration).
• Keep the low ESR input capacitor, C
IN
(labeled as C7 in
Figure 76), close to VIN and GND. This minimizes noise
injected into the part from board parasitic inductance.
• Keep the high current path from C
IN
(labeled as C7 in
Figure 76) through the L1 inductor to SW and GND as
short as possible.
• Keep the high current path from VIN through L1, the
rectifier (D1) and the output capacitor, C
OUT
(labeled as
C4 in Figure 76) as short as possible.
• Keep high current traces as short and as wide as possible.
• Place the feedback resistors as close to FB as possible to
prevent noise pickup. Connect the ground of the feedback
network directly to an AGND plane that makes a Kelvin
connection to the GND pin.
• Place the compensation components as close as possible to
COMP. Connect the ground of the compensation network
directly to an AGND plane that makes a Kelvin connection
to the GND pin.
• Connect the softstart capacitor, C
SS
(labeled as C1 in
Figure 76) as close to the device as possible. Connect the
ground of the softstart capacitor to an AGND plane that
makes a Kelvin connection to the GND pin.
• Avoid routing high impedance traces from the compensa-
tion and feedback resistors near any node connected to SW
or near the inductor to prevent radiated noise injection.