Datasheet

EVAL-ADP1612/ADP1613
Rev. A | Page 5 of 8
EVALUATION BOARD SCHEMATIC AND LAYOUT
ADP1612/
ADP1613
U1
6
3
7
8
5
2
1
4
VIN
EN
FREQ
SS
SW
FB
COMP
GND
L1 SW
C1
C4
C5 C6
C7
FREQ
R4
V
IN
C8 C9
C3
C2
R3
R1
R2
D1
08527-008
V
OUT
GND
EN
Figure 7. ADP1612/ADP1613Boost Application Evaluation Board Schematic
08527-009
Figure 8. ADP1612/ADP1613 Boost Application PCB Top Layer
08527-010
Figure 9. ADP1612/ADP1613 Boost Application PCB Bottom Layer
LAYOUT GUIDELINES
For high efficiency, good regulation, and stability, a well-
designed printed circuit board (PCB) layout is essential.
Use the following guidelines when designing PCBs:
• Keep the low ESR input capacitor, C
IN
(labeled as C7 in
Figure 8), close to VIN and GND. This minimizes noise
injected into the part from board parasitic inductance.
• Keep the high current path from C
IN
(labeled as C7 in
Figure 8) through the L1 inductor to SW and GND as
short as possible.
• Keep the high current path from VIN through L1, the
rectifier (D1), and the output capacitor, C
OUT
(labeled as
C4 in Figure 8), as short as possible.
• Keep high current traces as short and as wide as possible.
• Place the feedback resistors as close to FB as possible to
prevent noise pickup. Connect the ground of the feedback
network directly to an AGND plane to make a Kelvin
connection to the GND pin.
• Place the compensation components as close as possible to
COMP. Connect the ground of the compensation network
directly to an AGND plane that makes a Kelvin connection
to the GND pin.
• Connect the soft start capacitor, C
SS
(labeled as C1 in
Figure 8), as close to the device as possible. Connect the
ground of the soft start capacitor to an AGND plane that
makes a Kelvin connection to the GND pin.
• Avoid routing high impedance traces from the compensa-
tion and feedback resistors near any node connected to SW
or near the inductor to prevent radiated noise injection.