Datasheet

ADP1610
Rev. A | Page 17 of 20
LAYOUT PROCEDURE
To get high efficiency, good regulation, and stability, a well-
designed PCB layout is required. Where possible, use the
sample application board layout as a model.
When designing PCBs the following guidelines are to be used
(see Figure 2):
•
The low ESR input capacitor (C
IN
) is to be kept close to IN
and GND.
•
The high current path from C
IN
through the inductor L1 to
SW and PGND is to be kept as short as possible.
•
The high current path from C
IN
through L1, the rectifier
D1, and the output capacitor C
OUT
is to be kept as short as
possible.
•
High current traces are to be kept as short and as wide as
possible.
•
The feedback resistors are to be placed as close to the FB
pin as possible to prevent noise pickup.
•
The compensation components are to be placed as close as
possible to COMP.
•
To prevent radiated noise injection, high impedance traces
are not to be routed near any node connected to SW or
near the inductor.
04472-027
Figure 31. Sample Application Board (Bottom Layer)
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Figure 32. Sample Application Board (Top Layer)
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Figure 33. Sample Application Board (Silkscreen Layer)