Datasheet

UG-488 Evaluation Board User Guide
Rev. 0 | Page 4 of 8
EVALUATION BOARD SCHEMATIC AND LAYOUT
VIN
ADP1607
(U1)
ADP1607ACPZN-R7
ADP1607ACPZN001-R7
VIN
EN
L1
EN
GND
FB
SW
VOUT
R1
R2
C2 C1
SW
C3
C4
VOUT
GND
1
5
6
4
3
2
11089-005
Figure 5. ADP1607 Boost Application Evaluation Board Schematic
11089-006
Figure 6. ADP1607 Boost Application Printed Circuit Board (PCB) Top Layer
11089-007
Figure 7. ADP1607 Boost Application PCB Bottom Layer
LAYOUT GUIDELINES
For high efficiency, good regulation, and stability, a well-
designed printed circuit board layout is required.
Use the following guidelines when designing printed
circuit boards.
• Keep the low ESR input capacitor, C1, close to VIN and
GND. This minimizes noise injected into the part from
board parasitic inductance.
• Keep the high current path from C1 through the L1
inductor to SW as short as possible.
• Place the feedback resistors, R1 and R2, as close to FB as
possible to prevent noise pickup. Connect the ground of
the feedback network directly to an AGND plane that
makes a Kelvin connection to the GND pin.
• Avoid routing high impedance traces from feedback
resistors near any node connected to SW or near the
inductor to prevent radiated noise injection.
• Keep the low ESR output capacitor, C3, close to VOUT and
GND. This minimizes noise injected into the part from
board parasitic inductance.
• Connect Pin 7 (EPAD) and GND to a large copper plane
for proper heat dissipation.