Datasheet

ADP1053 Data Sheet
Rev. A | Page 8 of 84
Parameter Test Conditions/Comments Min Typ Max Unit
SERIAL BUS TIMING See Figure 3
Clock Frequency 100 400 kHz
Glitch Immunity, t
SW
50 ns
Bus Free Time, t
BUF
1.3 µs
Start Setup Time, t
SU;STA
0.6 µs
Stop Setup Time, t
SU;STO
0.6 µs
Start Hold Time, t
HD;STA
0.6 µs
SCL Low Time, t
LOW
0.6 µs
SCL High Time, t
HIGH
0.6 µs
SCL, SDA Rise Time, t
R
20 ns
SCL, SDA Fall Time, t
F
20 ns
Data Setup Time, t
SU;DAT
100 ns
Data Hold Time, t
HD;DAT
Read 125 ns
Write 300 ns
EEPROM
EEPROM Update Time
Time from update command to
EEPROM update completed (T
J
= 25°C)
40 ms
Reliability
Endurance
1
T
J
= 85°C 10,000 Cycles
T
J
= 125°C 1000 Cycles
Data Retention
2
T
J
= 85°C 20 Years
T
J
= 125°C 10 Years
1
Endurance is qualified as per JEDEC Standard 22, Method A117, and is measured at −40°C, +25°C, +85°C, and +125°C. Endurance conditions are subject to change
pending EEPROM qualification.
2
Retention lifetime equivalent at junction temperature (T
J
) = 125°C as per JEDEC Standard 22, Method A117. The derated lifetime is subject to change pending EEPROM
qualification.
10241-003
SCL
SD
A
PS
t
BUF
t
HD;STA
t
HD;DAT
t
HIGH
t
SU;DAT
t
HD;STA
t
SU;STA
t
SU;STO
t
LOW
t
R
t
F
SP
Figure 3. Serial Bus Timing Diagram