Datasheet

Data Sheet ADP1053
Rev. A | Page 75 of 84
Table 115. Register 0xFE7A—Channel B PSON Setting
Bits Bit Name R/W Description
7 PSON_B polarity R/W Setting this bit inverts the polarity of the PSON_B pin signal when hardware PSON_B is used.
0 = normal mode. A high signal on the PSON_B pin turns on Channel B.
1 = inverted. A low signal on the PSON_B pin turns on Channel B.
6 Software PSON_B R/W When software PSON_B is used, setting this bit turns on Channel B.
These bits specify which signal or signals are used as the PSON_B control.
Bit 5 Bit 4 PSON_B Control Selection
0 0 Always on. Channel B is always on.
0 1 Hardware PSON_B. The PSON_B pin turns Channel B on and off.
1 0 Software PSON_B. Bit 6 turns Channel B on and off.
[5:4]
PSON_B control
hardware/software
selection
R/W
1 1
Software and hardware PSON_B. Both the PSON_B pin and Bit 6 must be set
to turn on Channel B.
These bits specify the delay from when the PSON_B signal is set to when the soft start of Channel B begins.
Bit 3 Bit 2 Typical Delay Time
0 0 0 ms
0 1 50 ms
1 0 250 ms
[3:2] PSON_B delay R/W
1 1 1 sec
These bits specify the delay from when the PSON_B signal is cleared to when Channel B is turned off.
Bit 1 Bit 0 Typical Delay Time
0 0 0 ms
0 1 50 ms
1 0 250 ms
[1:0] PSOFF_B delay R/W
1 1 1 sec
Table 116. Register 0xFE7B—Additional Flag Reenable Delay and Channel C PSON Setting
Bits Bit Name R/W Description
7
Channel C
additional flag
reenable delay
R/W
This bit specifies whether an additional PSON_C delay is added to the reenable delay after a flag is
cleared and before Channel C begins a soft start.
0 = no additional delay is added to the reenable delay.
1 = additional PSON_C delay is added to the reenable delay.
6
Channel B
additional flag
reenable delay
R/W
This bit specifies whether an additional PSON_B delay is added to the reenable delay after a flag is
cleared and before Channel B begins a soft start.
0 = no additional delay is added to the reenable delay.
1 = additional PSON_B delay is added to the reenable delay.
5
Channel A
additional flag
reenable delay
R/W
This bit specifies whether an additional PSON_A delay is added to the reenable delay after a flag is
cleared and before Channel A begins a soft start.
0 = no additional delay is added to the reenable delay.
1 = additional PSON_A delay is added to the reenable delay.
4
PSON_C control
selection
R/W 0 = Channel C is always on.
1 = Either PSON_A or PSON_B must be set to turn on Channel C.
These bits specify the delay from when the PSON_C signal is set to when the soft start of Channel C begins.
Bit 3 Bit 2 Typical Delay Time
0 0 0 ms
0 1 50 ms
1 0 250 ms
[3:2] PSON_C delay R/W
1 1 1 sec
These bits specify the delay from when the PSON_C signal is cleared to when Channel C is turned off.
Bit 1 Bit 0 Typical Delay Time
0 0 0 ms
0 1 50 ms
1 0 250 ms
[1:0] PSOFF_C delay R/W
1 1 1 sec