Datasheet

ADP1053 Data Sheet
Rev. A | Page 72 of 84
Table 107. Register 0xFE72—Balance Control Settings
Bits Bit Name R/W Description
7
Channel selection for
volt-second balance
control
R/W Setting this bit selects Channel A or Channel C for volt-second balance control.
0 = use Channel C for volt-second balance control.
1 = use Channel A for volt-second balance control.
6
Volt-second balance
control limit
R/W This bit sets the modulation limit on the duty cycles from the volt-second control circuit.
0 = maximum volt-second control modulation is ±160 ns.
1 = maximum volt-second control modulation is ±80 ns.
These bits set the volt-second balance control loop gain.
Bit 5 Bit 4 Volt-Second Balance Control Loop Gain
0 0 1
0 1 4
1 0 16
[5:4]
Volt-second balance
loop gain
R/W
1 1 64
3
Sensing selection for
current balance
R/W Setting this bit selects CS1_A/CS1_B or CS2_A/CS2_B for current balance control.
0 = use CS2_A/CS2_B for current balance control.
1 = use CS1_A/CS1_B for current balance control.
2
Current balance
control limit
R/W This bit sets the modulation limit on the duty cycles from the current control circuit.
0 = maximum current control modulation is ±160 ns.
1 = maximum current control modulation is ±80 ns.
These bits set the current balance control loop gain.
Bit 1 Bit 0 Current Balance Control Loop Gain
0 0 1
0 1 4
1 0 16
[1:0]
Current balance loop
gain
R/W
1 1 64
TEMPERATURE SENSE AND PROTECTION SETTING REGISTERS
Table 108. Register 0xFE73—RTD1 Gain Trim
Bits Bit Name R/W Description
7 Gain polarity R/W 1 = negative gain is introduced.
0 = positive gain is introduced.
[6:0] RTD1 gain trim R/W This value calibrates the RTD1 sensing gain (see the RTD1, RTD2, OTP1, and OTP2 Trim section).
Table 109. Register 0xFE74—RTD2 Gain Trim
Bits Bit Name R/W Description
7 Gain polarity R/W 1 = negative gain is introduced.
0 = positive gain is introduced.
[6:0] RTD2 gain trim R/W This value calibrates the RTD2 sensing gain (see the RTD1, RTD2, OTP1, and OTP2 Trim section).