Datasheet

ADP1053 Data Sheet
Rev. A | Page 68 of 84
SR AND CHANNEL C SOFT START SETTING REGISTERS
Table 97. Register 0xFE67—Synchronous Rectifier (SR) Soft Start
Bits Bit Name R/W Description
[7:6] Reserved R/W Reserved.
When an SR PWM output is configured to turn on in a soft start manner (using Bits[3:0]), the
rising edge of the output moves left in steps of 40 ns. These bits specify how many switching
cycles are required to move the SR PWM output left in 40 ns.
Bit 5 Bit 4 SR Soft Start Timing
0 0 SR PWM output changes 40 ns in 1 switching cycle
0 1 SR PWM output changes 40 ns in 4 switching cycles
1 0 SR PWM output changes 40 ns in 16 switching cycles
[5:4] SR soft start timing R/W
1 1 SR PWM output changes 40 ns in 64 switching cycles
3 OUT8 SR soft start R/W Setting this bit enables SR soft start for OUT8.
2 OUT7 SR soft start R/W Setting this bit enables SR soft start for OUT7.
1 OUT4 SR soft start R/W Setting this bit enables SR soft start for OUT4.
0 OUT3 SR soft start R/W Setting this bit enables SR soft start for OUT3.
Table 98. Register 0xFE68—Channel C Soft Start
Bits Bit Name R/W Description
7
OUT1, OUT2, OUT5,
and OUT6 edges
R/W
When this bit is set, the falling edges of OUT1, OUT2, OUT5, and OUT6 always occur after the
rising edges in one cycle during a soft start.
6
OUT3, OUT4, OUT7,
and OUT8 edges
R/W This bit is valid only when Bit 7 is set to 1.
0 = rising edges of OUT3, OUT4, OUT7, and OUT8 always occur after the falling edges in one
cycle during a soft start.
1 = falling edges of OUT3, OUT4, OUT7, and OUT8 always occur after the rising edges in one
cycle during a soft start.
These bits determine the duty cycle ramp rate during soft start for the PWM outputs assigned
to Channel C. The duty cycle ramp rate is set to 40 ns per 1, 2, 4, or 8 switching cycles.
Bit 5 Bit 4 Channel C Soft Start Ramp Rate
0 0 PWM outputs change 40 ns in 1 switching cycle
0 1 PWM outputs change 40 ns in 2 switching cycles
1 0 PWM outputs change 40 ns in 4 switching cycles
[5:4]
Channel C soft start
timing
R/W
1 1 PWM outputs change 40 ns in 8 switching cycles
3 Global variation R/W Setting this bit enables global variation during Channel C soft start.
0 = OUT1, OUT3, OUT5, and OUT7 variation is independent of the OUT2, OUT4, OUT6, and
OUT8 variation during soft start.
1 = all outputs use the time variation calculated by the OUT2 timing.
2
OUT2 soft start
variation
R/W This bit selects the variation of the OUT2 on time during Channel C soft start.
0 = variation of OUT2 during soft start is t
F2
− t
R2
.
1 = variation of OUT2 during soft start is t
S
− t
R2
, where t
S
is the switching cycle.
1
OUT1, OUT3, OUT5,
and OUT7 variation
selection
R/W
This bit selects which PWM output determines the variation of OUT1, OUT3, OUT5, and OUT7
during Channel C soft start. If Bit 3 = 1, the setting of this bit is ignored.
0 = rising and falling edges of OUT1 determine OUT1, OUT3, OUT5, and OUT7 variation.
1 = rising and falling edges of OUT3 determine OUT1, OUT3, OUT5, and OUT7 variation.
0
OUT2, OUT4, OUT6,
and OUT8 variation
selection
R/W
This bit selects which PWM output determines the variation of OUT2, OUT4, OUT6, and OUT8
during Channel C soft start. If Bit 3 = 1, the setting of this bit is ignored.
0 = rising and falling edges of OUT2 determine OUT2, OUT4, OUT6, and OUT8 variation.
1 = rising and falling edges of OUT4 determine OUT2, OUT4, OUT6, and OUT8 variation.