Datasheet

Data Sheet ADP1053
Rev. A | Page 67 of 84
SYNCHRONIZATION SETTING REGISTERS
If the synchronization cycle for Channel A, Channel B, or Channel C is t
S
, and t
S
is programmed to be synchronized to the switching cycle,
t
SYNC
, the on times of the PWM outputs in this channel remain the same. For example, if OUT
X
and OUT
Y
are assigned to Channel C and
OUT
Y
is programmed for a 180°C phase shift, the difference between the falling edge of OUT
X
and the rising edge of OUT
Y
changes to
t
SYNC
/2 − t
FX
, as shown on the left side of Figure 44. If the timing of the outputs is critical—for example, when OUT
X
and OUT
Y
drive two
switches in a totem-pole structure—the operation of the power stage may be significantly affected.
Register 0xFE66 enables PWM output edge adjustment for OUT1 to OUT8. When the appropriate bit is set in Register 0xFE66, an
adjustment of (t
S
− t
SYNC
)/2 is made on both edges of the corresponding PWM output. It is important to enable output adjustment for the
complementary OUT
X
/ OUT
Y
pairs. With output edge adjustment set on both OUT
X
and OUT
Y
(as shown on the right side of Figure 44),
the dead time between the falling edge of OUT
X
and the rising edge of OUT
Y
is kept the same at t
S
/2 − t
FX
.
t
FX
t
FX
– ( t
S
– t
SYNC
)/2
t
FY
t
FY
– ( t
S
– t
SYNC
)/2
t
SYNC
/2 t
SYNC
/2 t
SYNC
t
SYNC
t
0
t
0
OUT
X
OUT
Y
OUT
X
OUT
Y
t
SYNC
/2 – t
FX
t
S
/2 – t
FX
t
S
/2 – t
FY
t
SYNC
/2 – t
FY
10241-049 SYNCHRONIZATION WITH NO EDGE ADJUSTMENT ON t
FX
AND t
FY
SYNCHRONIZATION WITH EDGE ADJUSTMENT ON t
FX
AND t
FY
Figure 44. PWM Output Edge Adjustment in Channel C Synchronization
Table 95. Register 0xFE65—OUT1 and OUT2 Shutdown in Channel C Synchronization
Bits Bit Name R/W Description
7 OUT2 shutdown R/W
Setting this bit shuts down OUT2 at the start of the OUT1 switching cycle. If OUT2 is not
assigned to Channel C, this bit must be set to 0.
6 OUT1 shutdown R/W
Setting this bit shuts down OUT1 at the start of the OUT2 switching cycle. If OUT1 is not
assigned to Channel C, this bit must be set to 0.
[5:0] Reserved R/W Reserved.
Table 96. Register 0xFE66—OUT1 Through OUT8 Dead Time Adjustment in Synchronization
Bits Bit Name R/W Description
7 OUT8 adjustment R/W Setting this bit adjusts both edges of OUT8 by (t
S
− t
SYNC
)/2.
6 OUT7 adjustment R/W Setting this bit adjusts both edges of OUT7 by (t
S
− t
SYNC
)/2.
5 OUT6 adjustment R/W
Setting this bit adjusts both edges of OUT6 by (t
S
− t
SYNC
)/2.
4 OUT5 adjustment R/W
Setting this bit adjusts both edges of OUT5 by (t
S
− t
SYNC
)/2.
3 OUT4 adjustment R/W
Setting this bit adjusts both edges of OUT4 by (t
S
− t
SYNC
)/2.
2 OUT3 adjustment R/W
Setting this bit adjusts both edges of OUT3 by (t
S
− t
SYNC
)/2.
1 OUT2 adjustment R/W
Setting this bit adjusts both edges of OUT2 by (t
S
− t
SYNC
)/2.
0 OUT1 adjustment R/W Setting this bit adjusts both edges of OUT1 by (t
S
− t
SYNC
)/2.