Datasheet

Data Sheet ADP1053
Rev. A | Page 17 of 84
Voltage Feedback Sensing (VS+_A/VS+_B, VS−_A/VS−_B)
VS_A and VS_B are used for the control, monitoring, and
undervoltage protection (UVP) of the remote output voltage
of Channel A and Channel B, respectively. VS_A and VS_B are
differential inputs; they function as the main feedback sense
points for the control loop.
The VS_A/VS_B sense points on the power rail require an
external resistor divider to bring the nominal voltage to 1 V
at the VS pins (see Figure 11). This voltage provides the best
accuracy for the ADC reading.
VS_A/VS_B use ADC1 for the high accuracy feedback loop and
ADC2 for the high speed feedback loop.
ADCs
Σ- ADCs have a resolution of one bit and operate differently
from traditional flash ADCs. The equivalent resolution obtain-
able depends on how long the output bit stream of the Σ-
ADC is sampled.
Σ- ADCs also differ from Nyquist rate ADCs in that the quan-
tization noise is not uniform across the frequency spectrum. At
lower frequencies the noise is lower, and at higher frequencies
the noise is higher (see Figure 12).
MAGNITUDE
FREQUENCY
NYQUIST ADC
NOISE
Σ-∆ ADC
NOISE
10241-050
Figure 12. Noise Performance for Nyquist Rate and Σ-Δ ADCs
Two types of Σ- ADCs are used in the feedback loop of the
ADP1053: a low frequency ADC and a high frequency ADC.
The low frequency ADC runs at approximately 1.56 MHz. For a
specified bandwidth, the equivalent resolution can be calculated
as follows:
ln(1.56 M/BW)/ln(2) = N bits
For example, at a bandwidth of 95 Hz, the equivalent
resolution/noise is
ln(1.5 M/95)/ln(2) = 14 bits
At a bandwidth of 1.5 kHz, the equivalent resolution/noise is
ln(1.56 M/1.5 k)/ln(2) = 10 bits
The high frequency ADC has a clock of 25 MHz. It is comb
filtered and outputs at the switching frequency (f
SW
) into the
digital filter.
The equivalent resolution for some sample frequencies is listed
in Table 7.
Table 7. Equivalent Resolution for High Frequency ADC
at Various Switching Frequencies
f
SW
(kHz) High Frequency ADC Resolution
48.8 9 bits
97.7 8 bits
195.3 7 bits
390.6 6 bits
The high frequency ADC has a range of ±10 mV. With the
switching frequency (f
SW
) set to 200 kHz, the quantization noise
is 0.156 mV, which is one LSB (2 × 10 mV/2
7
= 0.156 mV).
Increasing f
SW
to 400 kHz increases the quantization noise
to 0.3125 mV (1 LSB = 2 × 10 mV/2
6
= 0.3125 mV).
OVP Sensing (OVP_A, OVP_B)
OVP_A and OVP_B are used for overvoltage protection of
Channel A and Channel B, respectively. They are referenced
to PGND_A and PGND_B.
The OVP_A/OVP_B sense points on the power rail require an
external resistor divider to bring the nominal voltage to 1 V at the
OVP_A/OVP_B pins (see Figure 11). This divided-down signal is
internally fed into a comparator. The output of the comparator
goes to the OVP fault flags. The OVP threshold level can be pro-
grammed from 0.75 V to 1.5 V. For more information about the
OVP flags, see the Overvoltage Protection (OVP) Flags section.
CURRENT SENSE
The ADP1053 has five separate current sense inputs: CS, CS1_A,
CS1_B, CS2_A, and CS2_B. These inputs are used to protect the
power supply when the current exceeds the preset current limit.
The registers that configure the current sensing inputs must be
calibrated to remove errors due to external components. For
more information, see the Power Supply Calibration and Trim
section.
CS and CS1 (CS1_A/CS1_B) Sensing
CS1_A and CS1_B are typically used for the monitoring and
protection of Channel A and Channel B, respectively, whereas
CS is used for the unregulated Channel C. Generally, the current
inputs are sensed through a current transformer (CT). The input
signals at the pins are fed into ADCs for current monitoring.
The valid input range of these ADCs is from 0 V to 1.4 V. The
input signal is also fed into a comparator for fast overcurrent
protection (fast OCP). Typical configurations for current
sensing are shown in Figure 13 and Figure 14.