3-Channel Digital Power Supply Controller ADP1053 Data Sheet FEATURES GENERAL DESCRIPTION Configurable 8-PWM engine with up to 3 channels 2 independent digitally controlled channel outputs Voltage mode PWM control with 625 ps resolution Remote voltage sensing on both channels Programmable compensation filters Voltage feedforward option Flexible start-up sequencing and tracking Switching frequency: 50 kHz to 625 kHz Frequency synchronization Independent channel protections: OVP and OCP 2 independent OTP c
ADP1053 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 ACSNS Flag................................................................................. 28 Applications....................................................................................... 1 Overcurrent Protection (OCP) Flags ...................................... 28 General Description .....................................................................
Data Sheet ADP1053 PMBus Command Set (Supported by the ADP1053) ................42 Manufacturer-Specific Extended Command List .......................44 Manufacturer-Specific Extended Command Register Descriptions .....................................................................................50 PMBus Command Descriptions ...................................................46 Flag Configuration Registers.....................................................50 CLEAR_FAULTS Command...................
ADP1053 Data Sheet The ADP1053 provides local and remote differential sensing of the output voltage, which is converted to the digital domain using high speed, high resolution Σ-Δ converters. The proprietary conversion system maximizes the bandwidth of the converter and minimizes output noise due to digital quantization error, thus dramatically reducing the power consumption of the digital controller.
Data Sheet ADP1053 SPECIFICATIONS VDD = 3.0 V to 3.6 V, TA = −40°C to +125°C, unless otherwise noted. FSR = full-scale range. Table 1.
ADP1053 Parameter AC SENSE Input Voltage Input Voltage FSR ACSNS ADC Valid Input Voltage Range ADC Register Update Rate Resolution Measurement Accuracy Data Sheet Test Conditions/Comments Min Typ Max Unit Voltage from ACSNS to AGND 0 1 1.6 1.6 V V 0 1 800 11 1.
Data Sheet Parameter Accurate OCP Threshold Accuracy ADC Register Update Rate Current Sink (High Side) Current Source (Low Side) Fast Reverse Current Threshold (CS2+, CS2−) Threshold Accuracy Threshold Speed RTD1, RTD2 TEMPERATURE SENSE PINS Input Voltage Input Voltage FSR Source Current RTD1, RTD2 ADCs Valid Input Voltage Range ADC Register Update Rate Resolution Measurement Accuracy ADP1053 Test Conditions/Comments Min Typ Max Unit VOUT = 11 V, 5 kΩ level-shifting resistor VOUT = 0 V, 5 kΩ level-sh
ADP1053 Data Sheet Parameter SERIAL BUS TIMING Clock Frequency Glitch Immunity, tSW Bus Free Time, tBUF Start Setup Time, tSU;STA Stop Setup Time, tSU;STO Start Hold Time, tHD;STA SCL Low Time, tLOW SCL High Time, tHIGH SCL, SDA Rise Time, tR SCL, SDA Fall Time, tF Data Setup Time, tSU;DAT Data Hold Time, tHD;DAT Read Write EEPROM EEPROM Update Time Test Conditions/Comments See Figure 3 Min Typ Max Unit 100 400 50 100 kHz ns μs μs μs μs μs μs ns ns ns 125 300 ns ns 1.3 0.6 0.6 0.6 0.6 0.
Data Sheet ADP1053 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 2.
ADP1053 Data Sheet 40 39 38 37 36 35 34 33 32 31 RTD1 ADD RES AGND VDD VCORE DGND RTD2 FLGO/SYNO FLGI/SYNI PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADP1053 TOP VIEW (Not to Scale) 30 29 28 27 26 25 24 23 22 21 VS+_B VS–_B PGND_B OVP_B CS2–_B CS2+_B PGOOD_B CS1_B CS PSON_B 10241-004 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 SDA SCL 11 12 13 14 15 16 17 18 19 20 VS+_A 1 VS–_A 2 PGND_A 3 OVP_A 4 CS2–_A 5 CS2+_A 6 PGOOD_A 7 CS1_A 8 ACSNS 9 PSON_A 10 NOTES 1.
Data Sheet Pin No. 19 20 21 22 Mnemonic SDA SCL PSON_B CS 23 24 CS1_B PGOOD_B 25 CS2+_B 26 CS2−_B 27 28 29 OVP_B PGND_B VS−_B 30 31 VS+_B FLGI/SYNI 32 FLGO/SYNO 33 RTD2 34 DGND 35 36 VCORE VDD 37 38 AGND RES 39 ADD 40 RTD1 EP Exposed Pad ADP1053 Description PMBus/I2C Serial Data Input and Output (Open-Drain). This signal is referenced to AGND. PMBus/I2C Serial Clock Input and Output (Open-Drain). This signal is referenced to AGND. Power Supply On Input for Channel B.
ADP1053 Data Sheet APPLICATION CIRCUITS ACSNS CS1_A VIN = 36V DC TO 60V DC 100nH 3.3V 5V VDD = 10V Q1 iCoupler 7µH DRIVER Q2 ADuM3210 VDD = 10V 3.3V Q3 Q5 5V 3:5 DRIVER ADuM3210 VOUT A+ 48V/6.5A Q4 iCoupler VDD = 10V Q6 DRIVER Q7 LOAD VDD = 10V OUT2 DRIVER Q8 2mΩ CS1_A ACSNS OUT1 CS2–_A OUT2 CS2+_A OUT5 VS+_A OUT7 ADP1053 VS–_A OUT3 OUT4 OUT6 OUT8 CS1_B CS2–_B CS2+_B VS–_B VS+_B VOUT A– 1kΩ VOUT B+ DUPLICATE THE ABOVE SCHEMATICS FOR CHANNEL B VOUT B– Figure 5.
Data Sheet ADP1053 ACSNS CS1_A VIN = 36V DC TO 60V DC VDD = 10V Q1 DRIVER Q2 Q7 VDD = 10V Q3 Q5 3:5 DRIVER VOUT A+ 48V/4A Q4 LOAD Q6 VDD = 10V VOUT A– Q8 DRIVER VDD = 10V DRIVER 5V 3.3V OUT1 OUT3 OUT4 CS2–_A CS2+_A VS+_A VS–_A VDD = 10V OUT2 Q9 OUT6 DRIVER ADP1053 iCoupler 5V 3.3V OUT8 Q10 VOUT B+ 24V/5A LOAD VOUT B– OUT5 CS2–_B OUT7 CS2+_B VS+_B CS1_A VS–_B ACSNS Figure 6. Application Circuit 2—Two Output Channels with Only One Full-Bridge Rectifier Rev.
ADP1053 Data Sheet THEORY OF OPERATION PWM OUTPUTS (OUT1 TO OUT8) Timing of PWM Rising and Falling Edges The eight PWM outputs of the ADP1053 can be configured as two regulated channels with feedback control (Channel A and Channel B) and one additional unregulated channel with a fixed duty cycle (Channel C). The frequency of these channels can be individually programmed from 50 kHz to 625 kHz using Register 0xFE0A, Register 0xFE0B, and Register 0xFE0C, respectively.
Data Sheet ADP1053 Example Configuration of PWM Outputs tMOD_LIMIT Table 6 provides example register settings that configure the OUT1 and OUT2 outputs for Channel A. In this example, the switching frequency of Channel A is 208.3 kHz, that is, a 4.8 μs switching cycle (Register 0xFE0A = 0x15). OUTX tRX tFX GO Command Modulation Settings tMOD_LIMIT OUTY tRY tFY t0 tS/2 tS 3tS/2 10241-008 All eight PWM outputs work together.
ADP1053 Data Sheet FREQUENCY SYNCHRONIZATION Synchronization Output SYNI The FLGO/SYNO pin can be programmed to generate a synchronization reference output using Bit 3 of Register 0xFE0F. The pin outputs a 320 ns pulse-width signal, whose frequency follows either Channel A or Channel C (programmable using Bit 3 of Register 0xFE0E). To compensate for the propagation delays in the ADP1053 synchronization scheme, the SYNO signal has a 760 ns lead time before the start of the switching cycle.
Data Sheet ADP1053 Voltage Feedback Sensing (VS+_A/VS+_B, VS−_A/VS−_B) VS_A and VS_B are used for the control, monitoring, and undervoltage protection (UVP) of the remote output voltage of Channel A and Channel B, respectively. VS_A and VS_B are differential inputs; they function as the main feedback sense points for the control loop. The VS_A/VS_B sense points on the power rail require an external resistor divider to bring the nominal voltage to 1 V at the VS pins (see Figure 11).
ADP1053 Data Sheet For both high-side and low-side current sensing, it is recommended that a 500 pF to 1000 pF capacitor be connected from the CS2_A/CS2_B pins to AGND. VOUT DRIVER CS1_A/ CS1_B When using low-side resistor current sensing, as shown in Figure 15, the common-mode voltage at the sensing resistor is approximately 0 V. The current sources are 200 μA in low-side current sensing mode. Two matching 5 kΩ resistors are recommended.
Data Sheet ADP1053 The output voltage must be divided down using a resistor divider network (R1 and R2 in Figure 11) to set up a feedback voltage at the VS_A/VS_B pins. To convert the register value to an output voltage reference, use the following equation: The accurate ADC reading is used for CS2 overcurrent protection (OCP) and monitoring. For more information, see the CS2_A and CS2_B Accurate OCP Flags section and the CS2 (CS2_A/CS2_B) Readings section. VOUT = VS_Ref_Voltage_Value × 390.
ADP1053 Data Sheet DIGITAL FILTERS ACSNS AND INPUT FEEDFORWARD Channel A and Channel B each have an internal programmable digital filter. A Type III filter architecture is implemented in both digital filters. The low frequency gain, zero location, pole location, and high frequency gain can all be set individually to optimize the loop response. ACSNS has a low speed, high resolution ADC. This ADC samples at the same PWM switching frequency as Channel C.
Data Sheet ADP1053 LIGHT LOAD MODE AND PHASE SHEDDING VOUT The ADP1053 can be configured to disable PWM outputs under light load conditions based on the value of CS2_A and CS2_B. This function is programmed in Register 0xFE69 (for Channel A) and Register 0xFE6A (for Channel B) and can be used to implement phase shedding for multiphase operation.
ADP1053 Data Sheet Soft Start Ramp The unregulated Channel C can be programmed to be always on, or it can be programmed to be on when either PSON_A or PSON_B is on. This option is configured using Bit 4 of Register 0xFE7B. Software Reset The user can reset the ADP1053 power supply by writing the GO command to Register 0xFE88 (Bit 0 for Channel A; Bit 1 for Channel B).
Data Sheet ADP1053 Example Flag Timing During Soft Start In a fixed duty cycle, full-bridge application, OUT1 through OUT 4 are assigned to Channel C with soft start enabled. The switching frequency is 104.2 kHz, the switching cycle is 9.6 μs, tR1 = 0 μs, tF1 = 4 μs, tR2 = 4.8 μs, tF2 = 8.8 μs, tR3 = 4.2 μs, tF3 = 9.4 μs, tR4 = 9 μs, and tF4 = 4.6 μs. Therefore, tSS_C1 = tSS_C2 = 4 μs. The user can program which flags are active during the soft start. All flags are active at the end of the soft start.
ADP1053 Data Sheet Digital Filters During Soft Start A dedicated filter is used during soft start. The filter is disabled at the end of the soft start routine, after which the voltage loop digital filter is used. The soft start filter gain is programmable using Bits[1:0] of Register 0xFE3E and Register 0xFE3F. The soft start filter is used during the reference ramp time until the high frequency ADCs of VS_A/VS_B are settled.
Data Sheet ADP1053 POWER MONITORING AND FLAGS The ADP1053 has extensive system and fault monitoring capabilities for the sensed signals. The system monitoring functions include voltage, current, power, and temperature readings. The fault conditions include out-of-limit values for current, voltage, power, and temperature. The limits for the fault conditions are programmable.
ADP1053 Data Sheet The RTD1 and RTD2 value registers (Register 0xFED7 and Register 0xFED8, respectively) are updated every 10 ms. The ADP1053 stores every ADC sample for 10 ms and then outputs the average value at the end of the 10 ms period. The RTD1 and RTD2 ADCs have an input range of 0 V to 1.6 V and a resolution of 12 bits, which means that the LSB size is 1.6 V/4096 = 390.6 μV. The valid input range is 1.28 V, which means that the maximum ADC output code is limited to 1.28 V/390.6 μV = 3277.
Data Sheet ADP1053 CHANNEL A AND CHANNEL B DUTY CYCLE READINGS HOUSEKEEPING FLAGS The Channel A and Channel B duty cycle value registers (Register 0xFEDA and Register 0xFEDB, respectively) are updated every 10 ms. The duty cycle for Channel A and Channel B is calculated using the rising and falling edge timings of OUT1, OUT2, OUT5, or OUT6, depending on which PWM output is assigned to the corresponding channel.
ADP1053 Data Sheet Register 0xFEC1 for Channel B, and Register 0xFEC2 for Channel C). There is a 110 ns (max) propagation delay in the comparators. The response to the UVP_A and UVP_B flags can be programmed using Register 0xFE03. For more information, see the Protection Actions section and the Flag Configuration Registers section. During the soft start, PSON delay, and flag reenable time, the UVP_A and UVP_B flags are blanked.
Data Sheet ADP1053 Cycle-by-Cycle Limit Function for SR Outputs In addition to the CS_OCP, CS1_A_OCP, and CS1_B_OCP flags, a cycle-by-cycle limit function can be used. This function is triggered by the CS, CS1_A, and CS1_B OCP comparator output. For example, when the CS OCP comparator output is high, all PWM outputs assigned to Channel C are disabled for the remainder of the switching cycle. The outputs are reenabled at the start of the next switching cycle.
ADP1053 Data Sheet The FLGI/SYNI pin can be configured as a synchronization reference or as an external flag input. When this pin is configured as a flag input, an external fault signal can be sent to the pin. This flag is Bit 0 of Register 0xFEC2. The debounce time for this flag can be set to 0 μs or 100 μs using Register 0xFE0F. An additional PSON delay can be added to the reenable delay for each channel using Bits[7:5] of Register 0xFE7B.
Data Sheet ADP1053 When the ADP1053 registers one or more fault conditions, it stores the first flag in a dedicated register (Register 0xFECA for Channel A and Register 0xFECB for Channel B). The first flag ID represents the first flag that triggers a response and requires a soft start after the fault is resolved.
ADP1053 Data Sheet POWER SUPPLY CALIBRATION AND TRIM The ADP1053 allows the entire power supply to be calibrated and trimmed digitally in the production environment. It can calibrate items such as output voltage and trim for tolerance errors introduced by sense resistors, current transformers, and resistor dividers, as well as for its own internal circuitry. The part comes factory trimmed, but it can be retrimmed by the user to compensate for the errors introduced by external components in the system.
Data Sheet ADP1053 RTD1, RTD2, OTP1, AND OTP2 TRIM VDD The following procedure should be used: Place decoupling capacitors as close to the part as possible. A 330 nF capacitor from VDD to AGND is recommended. 1. 2. 3. Heat the thermistor or power supply to a known temperature that is equal to the OTP threshold.
ADP1053 Data Sheet PMBus/I2C COMMUNICATION The PMBus slave allows a device to interface to a PMBuscompliant master device, as specified by the PMBus Power System Management Protocol Specification (Revision 1.1, February 5, 2007). The PMBus slave is a 2-wire interface that can be used to communicate with other PMBus-compliant devices and is compatible in a multimaster, multislave bus configuration.
Data Sheet ADP1053 DATA TRANSFER Command Overview Format Overview Data transfer using the PMBus slave is established using PMBus commands. The PMBus specification requires that all PMBus commands start with a slave address with the R/W bit cleared (set to 0), followed by the command code. All PMBus commands supported by the ADP1053 follow one of the protocol types shown in Figure 31 through Figure 37.
ADP1053 Data Sheet 7-BIT SLAVE W ADDRESS A COMMAND CODE A BYTE COUNT = N A DATA BYTE 1 A DATA BYTE N A P 10241-141 S MASTER TO SLAVE SLAVE TO MASTER Figure 36. Block Write Protocol 7-BIT SLAVE W ADDRESS A COMMAND CODE A Sr 7-BIT SLAVE R ADDRESS A BYTE COUNT = N A DATA BYTE 1 A DATA BYTE N A P 10241-142 S MASTER TO SLAVE SLAVE TO MASTER Figure 37.
Data Sheet ADP1053 DATA TRANSMISSION FAULTS DATA CONTENT FAULTS Data transmission faults occur when two communicating devices violate the PMBus communication protocol, as specified in the PMBus specification. See the PMBus specification for more information about each fault condition. Data content faults occur when data transmission is successful, but the PMBus slave device cannot process the data that is received from the master device. Corrupted Data, PEC (Item 10.8.
ADP1053 Data Sheet EEPROM The ADP1053 has a built-in EEPROM controller that is used to communicate with the embedded 8K × 8-byte EEPROM. The EEPROM, also called Flash®/EE, is partitioned into two major blocks: the INFO block and the main block. The INFO block contains 128 8-bit bytes, and the main block contains 8K 8-bit bytes. The main block is further partitioned into 16 pages, each page containing 512 bytes.
Data Sheet Read two bytes from the INFO block. S 7-BIT SLAVE ADDRESS W A A Sr 7-BIT SLAVE ADDRESS A DATA BYTE 1 A DATA BYTE 2 R A A P Write to INFO Block 10241-031 BYTE COUNT = 0x80 0xF1 WRITE OPERATION (BYTE WRITE AND BLOCK WRITE) MASTER TO SLAVE SLAVE TO MASTER Note that the block read command to the INFO block can read a maximum of 128 bytes. However, only the first two bytes are used to store the first flag information.
ADP1053 Data Sheet EEPROM PASSWORD SAVING REGISTER SETTINGS TO THE EEPROM On power-up, the EEPROM is locked and protected from accidental writes or erases. Only reads from Page 2 to Page 15 are allowed when the EEPROM is locked. Before any data can be written (programmed) to the EEPROM, the EEPROM must be unlocked for write access. After it is unlocked, the EEPROM is opened for reading, writing, and erasing.
Data Sheet ADP1053 SOFTWARE GUI A free software GUI is available for programming and configuring the ADP1053. The GUI is designed to be intuitive and dramatically reduces power supply design and development time. For more information about the GUI, contact Analog Devices for the latest software and a user guide. 10241-044 The software includes filter design and power supply PWM topology windows.
ADP1053 Data Sheet PMBus COMMAND SET (SUPPORTED BY THE ADP1053) Table 12 lists the standard PMBus commands that are implemented on the ADP1053. Many of these commands are implemented in registers, which share the same hexadecimal value as the PMBus command code. Table 12.
Data Sheet ADP1053 Command Code 0xD1 Command Name EEPROM_CRC_CHKSUM SMBus Transaction Type Read byte Number of Data Bytes 1 0xD2 EEPROM_NUM_RD_BYTES Read/write byte 1 0xD3 0xD4 EEPROM_ADDR_OFFSET EEPROM_PAGE_ERASE Read/write word Write byte 2 1 0xD5 EEPROM_PASSWORD Write byte 1 0xD6 TRIM_PASSWORD Write byte 1 0xF1 EEPROM_INFO Read/write block Variable Description Return CRC checksum value from EEPROM download operation.
ADP1053 Data Sheet MANUFACTURER-SPECIFIC EXTENDED COMMAND LIST Table 13.
Data Sheet ADP1053 Command Name 0xFE58 OUT7 rising edge timing (MSBs) 0xFE59 OUT7 falling edge timing (MSBs) 0xFE5A OUT7 rising and falling edge timing (LSBs) 0xFE5B OUT7 settings 0xFE5C OUT8 rising edge timing (MSBs) 0xFE5D OUT8 falling edge timing (MSBs) 0xFE5E OUT8 rising and falling edge timing (LSBs) 0xFE5F OUT8 settings 0xFE60 PWM output pin disable GO Command Register 0xFE61 GO commands Balance Control Registers 0xFE62 Balance control on OUT1 and OUT2 0xFE63 Balance control on OUT3 and OUT4 0xFE64
ADP1053 Data Sheet PMBus COMMAND DESCRIPTIONS CLEAR_FAULTS COMMAND Command 0x03, send byte, no data. This command clears all fault bits in the STATUS_WORD register. WRITE_PROTECT COMMAND Table 14. Command 0x10—WRITE_PROTECT Bits 7 6 5 Bit Name Write Protect 1 Write Protect 2 Write Protect 3 R/W R/W R/W R/W [4:0] Reserved R Description Setting this bit disables writes to all commands except for WRITE_PROTECT.
Data Sheet ADP1053 STATUS_BYTE COMMAND This command returns the lower byte of the STATUS_WORD command. A value of 1 in this command indicates that a fault has occurred. Table 16. Command 0x78—STATUS_BYTE Bits 7 6 5 4 3 2 1 0 Bit Name BUSY PSON_OFF VOUT_OV IOUT_OC VIN_UV TEMPERATURE CML NONE_OF_THE_ ABOVE R/W R R R R R R R R Description Always reads 0. Not supported. Always reads 0. Not supported. Always reads 0. Not supported. Always reads 0. Not supported. Always reads 0. Not supported.
ADP1053 Data Sheet PMBUS_REVISION COMMAND Table 20. Command 0x98—PMBUS_REVISION (Default Value = 0x11) Bits [7:0] Bit Name Revision R/W R Description Return the revision of PMBus that the device is compliant with. MFR_ID COMMAND Table 21. Command 0x99—MFR_ID (Default Value = 0x41) Bits [7:0] Bit Name MFR_ID R/W R Description Return the manufacturer’s ID. MFR_MODEL COMMAND Table 22.
Data Sheet ADP1053 EEPROM_PAGE_ERASE COMMAND Table 27. Command 0xD4—EEPROM_PAGE_ERASE Bits [7:0] Bit Name Page erase R/W W Description Perform a page erase on the selected EEPROM page (Page 4 to Page 15). Wait 35 ms after each page erase operation. The EEPROM must first be unlocked. Page 0 and Page 1 are reserved for storing the default settings and user settings, respectively. The user cannot perform a page erase of Page 0 or Page 1.
ADP1053 Data Sheet MANUFACTURER-SPECIFIC EXTENDED COMMAND REGISTER DESCRIPTIONS FLAG CONFIGURATION REGISTERS Register 0xFE00 to Register 0xFE05 and Bits[3:0] of Register 0xFE06 are used to set the flag response and the resolution after the flag is cleared. Bits[7:6] of Register 0xFE06 set the global flag reenable delay time. Table 30.
Data Sheet ADP1053 Table 32. Register 0xFE06—Flag Reenable Delay, VDD_OV, and FLAGIN Configuration Bits [7:6] Bit Name Flag reenable delay R/W R/W 5 VDD_OV flag ignore R/W 4 VDD_OV flag debounce R/W [3:2] FLAGIN action R/W [1:0] Action after FLAGIN is cleared R/W Description These bits specify the global delay from when a flag is cleared to the soft start process. Bit 7 Bit 6 Typical Delay Time 0 0 250 ms 0 1 500 ms 1 0 1 sec 1 1 2 sec This bit enables or disables the VDD_OV flag.
ADP1053 Data Sheet Register 0xFE08 specifies whether volt-second balance control is blanked during the soft start of the channel that is configured for voltsecond balance (Channel A or Channel C). Bit 7 of Register 0xFE72 selects the channel for volt-second balance control. Register 0xFE08 also specifies whether to disable the SR outputs (OUT3, OUT4, OUT7, and OUT8) during the soft start of their assigned channel.
Data Sheet ADP1053 Bits [3:2] Bit Name PGOOD_A on debounce R/W R/W [1:0] PGOOD_A off debounce R/W Description These bits set the PGOOD_A on debounce time, that is, the time from when the PGOOD_A on condition is met to when the PGOOD_A flag is set. Bit 3 Bit 2 Typical PGOOD_A On Debounce Time 0 0 0 ms 0 1 200 ms 1 0 320 ms 1 1 600 ms These bits set the PGOOD_A off debounce time, that is, the time from when the PGOOD_A off condition is met to when the PGOOD_A flag is cleared.
ADP1053 Bits [5:0] Bit Name Switching frequency Data Sheet R/W R/W Description Bit 5 Bit 4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit 3 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit 2 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Rev.
Data Sheet ADP1053 When synchronization is enabled, the controller takes the SYNI signal, adds the tSYNC_DELAY, together with the 760 ns propagation delay, to generate the internal synchronization reference clock, as shown in Figure 40. Each channel then uses the reference clock (or a multiple of the reference clock if programmed in Register 0xFE0A, Register 0xFE0B, or Register 0xFE0C) to generate its own clock. Register 0xFE0D is used to set the tSYNC_DELAY time.
ADP1053 Data Sheet CHANNEL A/CHANNEL B CURRENT SENSE AND LIMIT SETTING REGISTERS Table 40. Register 0xFE10—CS1_A Gain Trim Bits 7 Bit Name Gain polarity R/W R/W [6:0] CS1_A gain trim R/W Description 1 = negative gain is introduced. 0 = positive gain is introduced. This value calibrates the CS1_A current sense gain. For more information, see the CS, CS1_A, and CS1_B Gain Trim section. Table 41.
Data Sheet ADP1053 Register 0xFE18 sets the CS2_A OCP threshold, and Register 0xFE19 sets the CS2_B OCP threshold. Table 48. Register 0xFE18 and Register 0xFE19—CS2_A OCP Threshold and CS2_B OCP Threshold Bits [7:0] Bit Name CS2_A/CS2_B OCP threshold R/W R/W Description The 8-bit OCP threshold set in this register is compared with Bits[15:8] in the CS2_A or CS2_B value register (Register 0xFED3 or Register 0xFED4).
ADP1053 Data Sheet Table 52. Register 0xFE1E—VS_A Reference Maximum Limit Bits [7:6] [5:0] Bit Name Reserved VS_A maximum reference R/W R/W R/W Description Reserved. This register sets the maximum limit of the Channel A output voltage reference. It sets the six MSBs for the reference limit. The factory default setting is 0x3F. Table 53. Register 0xFE1F—VS_B Reference Maximum Limit Bits [7:6] [5:0] Bit Name Reserved VS_B maximum reference R/W R/W R/W Description Reserved.
Data Sheet ADP1053 Table 60. Register 0xFE26—OVP_A Setting Bits [7:6] Bit Name OVP_A flag debounce time R/W R/W [5:0] OVP_A threshold R/W Description These bits set the OVP_A flag debounce time. Bit 7 Bit 6 Typical Debounce Time 0 0 0 μs 0 1 0.96 μs 1 0 2.24 μs 1 1 8 μs These bits set the threshold for the OVP_A analog comparator. This threshold is programmable from 0.75 V to 1.5 V. A setting of 0x00 corresponds to a 0.75 V threshold. A setting of 0x3F corresponds to a 1.5 V threshold.
ADP1053 Data Sheet SOFT START, DIGITAL FILTER, AND MODULATION SETTING REGISTERS Table 64. Register 0xFE2A—Channel A Soft Start Ramp Rate Bits [7:2] [1:0] Bit Name Reserved Channel A soft start ramp time R/W R/W R/W Description Reserved. These bits set the output reference ramp rate during soft start for Channel A. The ramp time is based on VREF = 2/3 full-scale range (FSR). Bit 1 Bit 0 Typical Soft Start Ramp Rate 0 0 1.75 ms 0 1 10.5 ms 21.0 ms 1 0 1 1 40.2 ms Table 65.
Data Sheet ADP1053 Table 68. Register 0xFE2E—Channel A Normal Mode Zero Setting Bits [7:0] Bit Name Channel A normal mode zero setting R/W R/W Description This register specifies the position of the zero in the feedback filter for Channel A in normal mode (see Figure 41). Table 69.
ADP1053 Data Sheet Table 77. Register 0xFE37—Channel B Light Load Mode Zero Setting Bits [7:0] Bit Name Channel B light load mode zero setting R/W R/W Description This register specifies the position of the zero in the feedback filter for Channel B in light load mode (see Figure 41). Table 78.
Data Sheet ADP1053 Table 83. Register 0xFE3D—Channel B Modulation Limit Bits [7:0] Bit Name Channel B modulation limit R/W R/W Description This register sets the maximum duty cycle modulation limit for PWM outputs in Channel B. The modulation limit is the maximum time variation for the modulated edges from the default timing (see Figure 42). The step size of an LSB depends on the switching frequency. Switching Frequency LSB Step Size 48.8 kHz to 86.8 kHz 80 ns 97.7 kHz to 183.8 kHz 40 ns 195.
ADP1053 Data Sheet PWM OUTPUT TIMING REGISTERS Figure 43 shows the timing of the rising and falling edges of the PWM outputs. Register 0xFE40 to Register 0xFE5F describe the implementation and programming of the eight PWM signals that are output from the ADP1053. In Figure 43, OUTX is an example of PWM timing without the 180° phase shift setting, and OUTY is an example of PWM timing with the 180° phase shift setting.
Data Sheet ADP1053 Table 89. Register 0xFE43/0xFE47/0xFE4B/0xFE4F/0xFE53/0xFE57/0xFE5B/0xFE5F—OUT1 to OUT8 Settings Bits 7 [6:5] Bit Name OUTX 180° delay Channel assignment R/W R/W R/W 4 Current/volt-second balance enable R/W 3 tRX modulation enable R/W 2 tRX modulation sign R/W 1 tFX modulation enable R/W 0 tFX modulation sign R/W Description Setting this bit adds a 180° delay to the timing of the OUTX edges.
ADP1053 Data Sheet BALANCE CONTROL REGISTERS Balance control is based on the modulation from volt-second balance control or dual-phase current balance control. For volt-second balance control, when the CS signal in the half cycle after the rising edge of OUT1 is higher than the CS signal in the half cycle after the rising edge of OUT2, the modulation value increases.
Data Sheet ADP1053 SYNCHRONIZATION SETTING REGISTERS If the synchronization cycle for Channel A, Channel B, or Channel C is tS, and tS is programmed to be synchronized to the switching cycle, tSYNC, the on times of the PWM outputs in this channel remain the same. For example, if OUTX and OUTY are assigned to Channel C and OUTY is programmed for a 180°C phase shift, the difference between the falling edge of OUTX and the rising edge of OUTY changes to tSYNC/2 − tFX, as shown on the left side of Figure 44.
ADP1053 Data Sheet SR AND CHANNEL C SOFT START SETTING REGISTERS Table 97. Register 0xFE67—Synchronous Rectifier (SR) Soft Start Bits [7:6] [5:4] Bit Name Reserved SR soft start timing R/W R/W R/W 3 2 1 0 OUT8 SR soft start OUT7 SR soft start OUT4 SR soft start OUT3 SR soft start R/W R/W R/W R/W Description Reserved. When an SR PWM output is configured to turn on in a soft start manner (using Bits[3:0]), the rising edge of the output moves left in steps of 40 ns.
Data Sheet ADP1053 LIGHT LOAD PWM DISABLE REGISTERS Table 99. Register 0xFE69—Channel A Light Load Mode PWM Output Disable Bits 7 6 5 4 3 2 1 0 Bit Name OUT8 disable OUT7 disable OUT6 disable OUT5 disable OUT4 disable OUT3 disable OUT2 disable OUT1 disable R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Setting this bit disables the OUT8 output when Channel A is in light load mode. Setting this bit disables the OUT7 output when Channel A is in light load mode.
ADP1053 Data Sheet Table 102. Register 0xFE6C—CS1_B Blanking Reference Edge Bits [7:4] 3 Bit Name Reserved OUT6 rising edge blanking R/W R/W R/W 2 OUT5 rising edge blanking R/W 1 OUT2 rising edge blanking R/W 0 OUT1 rising edge blanking R/W Description Reserved. This bit specifies whether the blanking time for the CS1_B OCP comparator is referenced to the rising edge of OUT6. 0 = no blanking at OUT6 rising edge. 1 = blanking time referenced to OUT6 rising edge.
Data Sheet ADP1053 Bits [3:2] Bit Name CS_OCP flag timeout R/W R/W [1:0] CS_OCP flag debounce time R/W Description These bits specify the number of consecutive switching cycles with OCP triggered that must occur before the CS_OCP flag is set. Bit 3 Bit 2 Fast OCP Flag Timeout 0 0 1 switching cycle 0 1 8 switching cycles 1 0 64 switching cycles 1 1 512 switching cycles These bits set the CS_OCP flag debounce time.
ADP1053 Data Sheet Table 107. Register 0xFE72—Balance Control Settings Bits 7 Bit Name Channel selection for volt-second balance control R/W R/W 6 Volt-second balance control limit R/W [5:4] Volt-second balance loop gain R/W 3 Sensing selection for current balance R/W 2 Current balance control limit R/W [1:0] Current balance loop gain R/W Description Setting this bit selects Channel A or Channel C for volt-second balance control. 0 = use Channel C for volt-second balance control.
Data Sheet ADP1053 Register 0xFE75 sets the OTP1 threshold value. The debounce time of the OTP1 flag is 100 ms. Table 110. Register 0xFE75—OTP1 Threshold Bits [7:0] Bit Name OTP1 threshold R/W R/W Description OTP1 threshold. This register, adding 0 as the MSB, results in a 9-bit threshold value. This 9-bit value is compared to the nine MSBs of the RTD1 value register (Register 0xFED7). If the OTP1 threshold is higher than the RTD1 ADC reading, the OTP1 flag is set.
ADP1053 Data Sheet Table 113. Register 0xFE78—ACSNS Setting Bits 7 Bit Name ACSNS flag included in PGOOD Debounce of ACSNS flag included in PGOOD R/W R/W [5:2] ACSNS threshold R/W [1:0] ACSNS flag debounce time R/W 6 R/W Description Setting this bit includes the ACSNS flag in the PGOOD_A and PGOOD_B flags. The debounce time for this function is set with Bit 6. This bit sets the debounce time of the ACSNS flag when it is included in the PGOOD_A and PGOOD_B flags. 0 = 0 ms. 1 = 2.6 ms.
Data Sheet ADP1053 Table 115. Register 0xFE7A—Channel B PSON Setting Bits 7 Bit Name PSON_B polarity R/W R/W 6 [5:4] Software PSON_B PSON_B control hardware/software selection R/W R/W [3:2] PSON_B delay R/W [1:0] PSOFF_B delay R/W Description Setting this bit inverts the polarity of the PSON_B pin signal when hardware PSON_B is used. 0 = normal mode. A high signal on the PSON_B pin turns on Channel B. 1 = inverted. A low signal on the PSON_B pin turns on Channel B.
ADP1053 Data Sheet RTD TRIM REGISTERS Table 117. Register 0xFE7C—RTD1 Offset Trim (MSB) Bits [7:2] 1 Bit Name Reserved Trim polarity R/W R/W R/W 0 RTD1 offset trim (MSB) R/W Description Reserved. 1 = negative gain is introduced. 0 = positive gain is introduced. This bit, together with Register 0xFE7D, sets the amount of offset trim that is applied to the RTD1 ADC reading. Table 118.
Data Sheet ADP1053 CUSTOMIZED REGISTERS Table 123. Register 0xFE82—Custom Register Bits [7:0] Bit Name Custom register R/W R/W Description This register is available to the user to store custom information. For example, this register can be used to store user software or hardware revision information. Table 124.
ADP1053 Data Sheet Table 126. Register 0xFE86 and Register 0xFE87—VS_A/VS_B Slew Rate for Output Voltage Adjustment Bits [7:4] [3:1] Bit Name Reserved Slew rate setting R/W R/W R/W 0 Slew rate adjust enable R/W Description Reserved. These bits specify the slew rate. Bit 3 Bit 2 Bit 1 Slew Rate 0 0 0 1.5625 mV/ms (4 LSB/ms) 0 0 1 3.125 mV/ms 0 1 0 6.25 mV/ms 0 1 1 12.
Data Sheet ADP1053 Table 129. Register 0xFE8A—OTW1/OTW2 Settings Bits 7 Bit Name OTW2 flag debounce R/W R/W 6 OTW2 triggers PGOOD_B R/W [5:4] OTW2 threshold R/W 3 OTW1 flag debounce R/W 2 OTW1 triggers PGOOD_A R/W [1:0] OTW1 threshold R/W Description This bit sets the OTW2 flag debounce time. 0 = 100 ms. 1 = 0 ms. This bit specifies whether the OTW2 flag triggers PGOOD_B. 0 = OTW2 does not trigger PGOOD_B. 1 = OTW2 triggers PGOOD_B. These bits set the OTW2 threshold.
ADP1053 Data Sheet Table 131. Register 0xFEC1—Flag Register 2 and Register 0xFEC6—Latched Flag Register 2 (1 = Fault, 0 = Normal Operation) Bits 7 Bit Name POWER_SUPPLY_B R/W R 6 PGOOD_B R 5 CS1_B_OCP R Description Channel B power supply is off and the PWM outputs are disabled. This bit stays high until PSON_B is asserted. Power-good fault on Channel B. This flag is set when the UVP_B, POWER_SUPPLY_B, EEPROM_CRC, or SOFTSTART_FILTER_B flag is set.
Data Sheet ADP1053 Table 134. Register 0xFEC4—Flag Register 5 and Register 0xFEC9—Latched Flag Register 5 (1 = Fault, 0 = Normal Operation) Bits [7:4] 3 2 1 Bit Name Reserved OTW2 OTW1 REVERSE_B R/W R R R R 0 REVERSE_A R Description Reserved. Temperature of Zone 2 is above the OTW2 threshold. Temperature of Zone 1 is above the OTW1 threshold. CS2_B reverse current falls below the CS2_B reverse current threshold. CS2_A reverse current falls below the CS2_A reverse current threshold.
ADP1053 Data Sheet VALUE REGISTERS Table 136. Register 0xFED0—CS Value Bits [15:4] Bit Name CS voltage value R/W R [3:0] Reserved R Description This register contains the 12-bit CS current information. The range of the CS input pin is from 0 V to 1.6 V. Each LSB corresponds to 390.6 μV. At 0 V input, the value in this register is 0. The nominal voltage at this pin is 1 V. At 1 V input, the value in these bits is 0xA00 (2560 decimal). Reserved. Table 137.
Data Sheet ADP1053 Table 143. Register 0xFED7—RTD1 Value Bits [15:4] Bit Name RTD1 temperature value R/W R [3:0] Reserved R Description This register contains the 12-bit RTD1 temperature information as determined from the RTD1 pin. The range of the RTD1 input pin is from 0 V to 1.6 V. Each LSB corresponds to 390.6 μV. At 0 V input, the value in this register is 0. The nominal voltage at this pin is 1 V. At 1 V input, the value in these bits is 0xA00 (2560 decimal). Reserved. Table 144.
ADP1053 Data Sheet OUTLINE DIMENSIONS 0.30 0.23 0.18 31 40 30 0.50 BSC 1 TOP VIEW 0.80 0.75 0.70 10 11 20 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 4.45 4.30 SQ 4.25 EXPOSED PAD 21 0.45 0.40 0.35 PIN 1 INDICATOR BOTTOM VIEW 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WJJD. 05-06-2011-A PIN 1 INDICATOR 6.10 6.00 SQ 5.90 Figure 45.
