Datasheet

Evaluation Board User Guide UG-320
Rev. A | Page 13 of 48
THEORY OF OPERATION
DURING STARTUP
The following steps briefly describe the start-up procedure of
the ADP1046 and the power supply and operation of the state
machine for the preprogrammed set of registers that are
included in the design kit.
1. After VDD (3.3 V) is applied to the ADP1046, it takes
approximately 20 µs for VCORE to reach 2.5 V. The digital
core is now activated and the contents of the registers are
downloaded in the EEPROM. The ADP1046 is now ready
for operation.
2. PSON is applied. The power supply begins the programmed
soft start ramp of 80 ms only when the logical AND of
hardware and software PSON is true (programmable).
3. Because the soft start from precharge setting is active, the
output voltage is sensed before the soft start ramp begins.
Depending on the output voltage level of the effective soft
start, the ramp is reduced by the proportional amount.
4. The OrFET power-on is dependent on the voltage
difference of VS1 and VS2. If the PSU is standalone, the
OrFET gate turns on at the beginning of the soft start ramp
when VS1 VS2 is less than or equal to the programmed
threshold in the GUI (see the OrFET Settings window in
the GUI, which is accessed by clicking OrFET Settings in
Figure 9). The output regulation is from VS3, and the
normal filter is in operation.
If the PSU is starting into a live bus already at 12 V, t h e
OrFET turns on only at the end of the soft start ramp when
the internal (or local) output voltage (VS1) climbs close to
the regulation point and VS1VS2 is greater than the
programmed threshold (threshold being a negative value
ranging from 384 mV to 0 mV). Prior to this, the soft start
filter is active, and the regulation/feedback path is through
VS1. When the OrFET turns on (GATE pin signal is toggled),
the feedback path is through VS3 and the compensation
filter changes to normal mode or light load filter (depending
on the load and light load threshold) in a time determined
by the filter transitioning speed (programmable 1 to 32
switching cycles).
5. The PSU is now running in a steady state and, depending
on the load condition, one or both phases are active (second
phase is on when the load current is greater than 14 A).
PGOOD1 and PGOOD2 turn on after the programmed
debounce.
6. If a fault is activated during the soft start or steady state,
the corresponding flag is set and the programmed action is
taken, such as PSU disable and reenable after 1 sec, SR
power-off, OrFET disable, and OUTAUX disable.
DURING STEADY STATE
The MOSFET drivers are powered using the auxiliary boost
converter from the main 12 V when the output is in regulation
before PSON is applied.
The second phase is turned on only when the load current
increases greater than 14 A. An asynchronous current detection
on CS2 averages the load current every 75 µs, and the part exits
light load mode.
If a fault such as a undervoltage protection (UVP), overvoltage
protection (OVP), CS2 overcurrent protection (OCP), or CS1
OCP occurs, the programmed action such as disable OrFET or
disable PWMs takes place after the debounce period. If the
PSU shuts down, the soft start ramp is initiated after the pro-
grammed delay.