Datasheet

ADP1046A Data Sheet
Rev. 0 | Page 86 of 88
Table 154. Register 0x49—OUTC Rising Edge Dead Time in Resonant Mode
Bits Bit Name R/W Description
[7:0] Δt
5
(rising edge dead
time of OUTC)
R/W This register sets Δt
5
, which is the difference between the rising edge of OUTC and the mid-
point of the switching cycle, t
B
. Each LSB corresponds to 5 ns of resolution. When the register
value is from 0x00 to 0x7F, the rising edge of OUTC is trailing t
B
. When the value is from 0x80
to 0xFF, the rising edge of OUTC is leading t
B
.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Δt
5
0 0 0 0 0 0 0 0 0 ns
0 0 0 0 0 0 0 1 5 ns trailing
… … … … … … … … …
0 1 1 1 1 1 1 1 635 ns trailing
1 0 0 0 0 0 0 0 640 ns leading
… … … … … … … … …
1 1 1 1 1 1 1 1 5 ns leading
Table 155. Register 0x4A—Burst Mode Operation in Resonant Mode
Bits
Bit Name
R/W
Description
[7:6] Burst mode enable R/W These bits are used to enable or disable burst mode operation.
Bit 7 Bit 6 Burst Mode
0 0 Disabled
0 1 Enabled for normal operation, but disabled during soft start
1 0 Disabled
1 1 Enabled for normal operation and during soft start
[5:0] Burst mode offset R/W These bits, along with the highest switching frequency limit, determine the threshold value for
enabling burst mode operation. For information about how to set this value, see the Light Load
Operation (Burst Mode) section. During burst mode, the PWM frequency is the maximum
frequency limit set in Register 0x46.
Table 156. Register 0x4B—OUTC Falling Edge Dead Time in Resonant Mode
Bits Bit Name R/W Description
[7:0] Δt
6
(falling edge dead
time of OUTC)
R/W This register sets Δt
6
, which is the leading time of the falling edge of OUTC from the end of the
switching cycle, t
C
. Each LSB corresponds to 5 ns of resolution.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Δt
6
(ns)
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1 5
… … … … … … … … …
1 1 1 1 1 1 1 1 1275
Table 157. Register 0x4D—OUTD Rising Edge Dead Time in Resonant Mode
Bits Bit Name R/W Description
[7:0] Δt
7
(rising edge dead
time of OUTD)
R/W This register sets Δt
7
, which is the difference between the rising edge of OUTD and the mid-
point of the switching cycle, t
B
. Each LSB corresponds to 5 ns of resolution. When the register
value is from 0x00 to 0x7F, the rising edge of OUTD is trailing t
B
. When the value is from 0x80
to 0xFF, the rising edge of OUTD is leading t
B
.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Δt
7
0
0
0
0
0
0
0
0
0 ns
0 0 0 0 0 0 0 1 5 ns trailing
… … … … … … … … …
0 1 1 1 1 1 1 1 635 ns trailing
1 0 0 0 0 0 0 0 640 ns leading
… … … … … … … … …
1 1 1 1 1 1 1 1 5 ns leading