Datasheet

Data Sheet ADP1046A
Rev. 0 | Page 77 of 88
Table 113. Register 0x79—SR Delay Compensation
Bits Bit Name R/W Description
[7:6] Reserved R/W Reserved.
[5:0] SR driver delay R/W These bits specify the 6-bit representation of the SR delay in steps of 5 ns.
000000 = 0 ns.
111111 = 63 ns × 5 ns = 315 ns.
Table 114. Register 0x7A—Filter Transitions
Bits Bit Name R/W Description
[7:6] Reserved R/W Reserved.
[5:3] HF ADC configuration R/W Set these bits to 001 at all times for proper operation.
2 Enable soft transition R/W Setting this bit enables a soft transition between filter settings to minimize output transients.
All four parameters of each filter are linearly transitioned to the new value.
[1:0] Transition speed R/W These bits set the transition speed from one filter to another. The filter changes in 32 steps;
each step is applied at the multiple of switching cycles (t
SW
) specified by these bits.
Bit 1 Bit 0
Speed (t
SW
= One Switching Cycle)
0 0 32 t
SW
(total transition time = 32 × 32 t
SW
= 1024 × t
SW
)
0 1 8 t
SW
(total transition time = 8 × 32 t
SW
= 256 × t
SW
)
1
0
2 t
SW
(total transition time = 64 × t
SW
)
1 1 1 t
SW
(total transition time = 32 × t
SW
)
Table 115. Register 0x7B—PGOOD1 Flag Masking
Bits Bit Name R/W Description
7 Soft start flag R/W If this bit is set to 1, the soft start flag is ignored by PGOOD1. This bit must be set to 0 to enable
proper PGOOD1 debounce timing after the end of the soft start ramp.
6 CS1 fast OCP R/W If this bit is set to 1, the CS1 fast OCP flag is ignored by PGOOD1.
5 CS1 accurate OCP R/W If this bit is set to 1, the CS1 accurate OCP flag is ignored by PGOOD1.
4 CS2 accurate OCP R/W If this bit is set to 1, the CS2 accurate OCP flag is ignored by PGOOD1.
3 UVP R/W If this bit is set to 1, the UVP flag is ignored by PGOOD1.
2 Local OVP (fast and
accurate)
R/W If this bit is set to 1, the local OVP flag is ignored by PGOOD1.
1 Load OVP R/W If this bit is set to 1, the load OVP flag is ignored by PGOOD1.
0 OrFET R/W If this bit is set to 1, the OrFET flag is ignored by PGOOD1.
Table 116. Register 0x7C—PGOOD2 Flag Masking
Bits Bit Name R/W Description
7 Soft start flag R/W If this bit is set to 1, the soft start flag is ignored by PGOOD2. This bit must be set to 0 to enable
proper PGOOD2 debounce timing after the end of the soft start ramp.
6 CS1 fast OCP R/W If this bit is set to 1, the CS1 fast OCP flag is ignored by PGOOD2.
5 CS1 accurate OCP R/W If this bit is set to 1, the CS1 accurate OCP flag is ignored by PGOOD2.
4 CS2 accurate OCP R/W If this bit is set to 1, the CS2 accurate OCP flag is ignored by PGOOD2.
3 UVP R/W If this bit is set to 1, the UVP flag is ignored by PGOOD2.
2 Local OVP (fast and
accurate)
R/W If this bit is set to 1, the local OVP flag is ignored by PGOOD2.
1 Load OVP R/W If this bit is set to 1, the load OVP flag is ignored by PGOOD2.
0 OrFET R/W If this bit is set to 1, the OrFET flag is ignored by PGOOD2.