Datasheet

Data Sheet ADP1046A
Rev. 0 | Page 75 of 88
SOFT START FILTER PROGRAMMING REGISTERS
Table 105. Register 0x71—Soft Start Digital Filter LF Gain Setting
Bits Bit Name R/W Description
[7:0]
LF gain setting
R/W
This register determines the low frequency gain of the loop response during soft start. The LF
gain is programmable over a 20 dB range (see Figure 58).
Table 106. Register 0x72—Soft Start Digital Filter Zero Setting
Bits
Bit Name
R/W
Description
[7:0] Zero setting R/W This register determines the position of the final zero during soft start (see Figure 58).
Table 107. Register 0x73—Soft Start Digital Filter Pole Setting
Bits Bit Name R/W Description
[7:0] Pole location R/W This register determines the position of the final pole during soft start (see Figure 58).
Table 108. Register 0x74—Soft Start Digital Filter HF Gain Setting
Bits Bit Name R/W Description
[7:0]
HF gain setting
R/W
This register determines the high frequency gain of the loop response during soft start. The HF
gain is programmable over a 20 dB range (see Figure 58).
EXTENDED FUNCTIONS REGISTERS
Table 109. Register 0x75—Voltage Line Feedforward
Bits Bit Name R/W Description
[7:4] Reserved R/W Reserved.
3 Disable feedforward
during soft start
R/W If voltage line feedforward is enabled, this bit disables it during the reference ramp-up (soft start).
This operation is gated by the filter GO bit (Register 0x7F[3]).
0 = feedforward enabled during soft start (recommended setting).
1 = feedforward disabled during soft start.
2
Feedforward enable
R/W
This bit enables the voltage line feedforward loop. This operation is gated by the filter GO bit
(Register 0x7F[3]).
0 = feedforward disabled.
1 = feedforward enabled.
[1:0] Gain setting R/W These bits set the gain for the voltage feedforward function.
Bit 1 Bit 0 Gain
0 0 1
0 1 0.875
1 0 0.75
1 1 0.5
Table 110. Register 0x76—Volt-Second Balance Settings (OUTA and OUTB Pins)
Bits Bit Name R/W Description
7 Modulate enable, t
1
R/W Setting this bit enables modulation from balance control on the OUTA rising edge, t
1
. It is
recommended that volt-second balance not be enabled on edges that are between 0 ns and
640 ns of the switching period.
6 t
1
sign R/W 0 = positive sign. Increase of balance control modulation moves t
1
right.
1 = negative sign. Increase of balance control modulation moves t
1
left.
5 Modulate enable, t
2
R/W Setting this bit enables modulation from balance control on the OUTA falling edge, t
2
. It is
recommended that volt-second balance not be enabled on edges that are between 0 ns and
640 ns of the switching period.
4 t
2
sign R/W 0 = positive sign. Increase of balance control modulation moves t
2
right.
1 = negative sign. Increase of balance control modulation moves t
2
left.
3 Modulate enable, t
3
R/W Setting this bit enables modulation from balance control on the OUTB rising edge, t
3
. It is
recommended that volt-second balance not be enabled on edges that are between 0 ns and
640 ns of the switching period.