Datasheet

Data Sheet ADP1046A
Rev. 0 | Page 73 of 88
Table 93. Register 0x5D—OUTx and SRx Pin Disable Settings
Bits Bit Name R/W Description
7 OUTAUX disable R/W Setting this bit disables the OUTAUX output.
6 SR2 disable R/W Setting this bit disables the SR2 output.
5 SR1 disable R/W Setting this bit disables the SR1 output.
4 OUTD disable R/W Setting this bit disables the OUTD output.
3 OUTC disable R/W Setting this bit disables the OUTC output.
2 OUTB disable R/W Setting this bit disables the OUTB output.
1 OUTA disable R/W Setting this bit disables the OUTA output.
0 GATE disable R/W Setting this bit disables the GATE output but does not affect the VSx feedback point.
Table 94. Register 0x5E—ACSNS Gain Trim
Bits Bit Name R/W Description
7 Gain polarity R/W 1 = negative gain is introduced.
0 = positive gain is introduced.
[6:0] ACSNS gain trim R/W These bits set the gain trim for the ACSNS ADC.
DIGITAL FILTER PROGRAMMING REGISTERS
Register 0x5F to Register 0x67 can be used to program the digital filters. It is recommended that the software GUI be used to program the
digital filters.
POLE LOCATION RANGE
ZERO
ZERO
RANGE
20dB
POLE
LF GAIN RANGE
20dB
20dB
HF GAIN
RANGE
100Hz 500Hz 1kHz 5kHz 10kHz
11012-036
Figure 58. Digital Filter Programmability
Table 95. Register 0x5F—Soft Start and Output Voltage Slew Rate Settings
Bits Bit Name R/W Description
[7:5] Soft start ramp R/W These bits determine the duration of the soft start ramp.
Bit 7 Bit 6 Bit 5 Ramp Duration
0 0 0 5 ms
0 0 1 10 ms
0 1 0 15 ms
0 1 1 20 ms
1 0 0 40 ms
1 0 1 50 ms
1
1
0
80 ms
1 1 1 100 ms
4 Soft start from
precharge
R/W Setting this bit to 1 enables the soft start from precharge function. When this function is enabled,
the soft start ramp starts from the value of the voltage detected on VS1 or VS3± (depending on
the OrFET status).
3 Reserved R/W Reserved.