Datasheet
ADP1046A Data Sheet
Rev. 0 | Page 70 of 88
Table 82. Register 0x52—SR1 Rising Edge Setting (SR1 Pin)
Bits Bit Name R/W Description
[7:4] t
9
R/W These bits contain the four LSBs of the 12-bit t
9
time. This value is always used with the eight
bits of Register 0x51, which contains the eight MSBs of the t
9
time. Each LSB corresponds to
5 ns resolution. The entire switching period is divided into 40 ns time steps. If the t
Rx
and t
Fx
of a
PWM edge occur within the same 40 ns time step, the PWM output is 0 V. If the t
Rx
and t
Fx
occur
in different 40 ns time steps, the PWM output is set to the programmed value. The absolute
maximum pulse width is t
PERIOD
− 5 ns. It is recommended that the SR1 rising edge not be set
between 80 ns and 115 ns when using the SR soft start.
3 Modulate enable R/W 1 = PWM modulation acts on the t
9
edge.
0 = no PWM modulation of the t
9
edge.
2 t
9
sign R/W 1 = negative sign. Increase of PWM modulation moves t
9
right.
0 = positive sign. Increase of PWM modulation moves t
9
left.
1 Reserved R/W Reserved.
0 SR soft start edge
control
R/W 0 = always allow SR edge crossing.
1 = allow SR edge crossing only during SR soft start (recommended).
Table 83. Register 0x53—SR1 Falling Edge Timing (SR1 Pin)
Bits Bit Name R/W Description
[7:0]
t
10
R/W
This register contains the eight MSBs of the 12-bit t
10
time. This value is always used with the top
four bits of Register 0x54, which contains the four LSBs of the t
10
time. Each LSB corresponds to
5 ns resolution. The entire switching period is divided into 40 ns time steps. If the t
Rx
and t
Fx
of a
PWM edge occur within the same 40 ns time step, the PWM output is 0 V. If the t
Rx
and t
Fx
occur
in different 40 ns time steps, the PWM output is set to the programmed value. The absolute
maximum pulse width is t
PERIOD
− 5 ns.
Table 84. Register 0x54—SR1 Falling Edge Setting (SR1 Pin)
Bits Bit Name R/W Description
[7:4] t
10
R/W These bits contain the four LSBs of the 12-bit t
10
time. This value is always used with the eight
bits of Register 0x53, which contains the eight MSBs of the t
10
time. Each LSB corresponds to
5 ns resolution. The entire switching period is divided into 40 ns time steps. If the t
Rx
and t
Fx
of a
PWM edge occur within the same 40 ns time step, the PWM output is 0 V. If the t
Rx
and t
Fx
occur
in different 40 ns time steps, the PWM output is set to the programmed value. The absolute
maximum pulse width is t
PERIOD
− 5 ns.
3 Modulate enable R/W 1 = PWM modulation acts on the t
10
edge.
0 = no PWM modulation of the t
10
edge.
2 t
10
sign R/W 1 = negative sign. Increase of PWM modulation moves t
10
right.
0 = positive sign. Increase of PWM modulation moves t
10
left.
1 SR soft start setting R/W 1 = SR signals perform a soft start every time that they are enabled.
0 = SR signals perform a soft start only the first time that they are enabled.
0 SR soft start enable R/W Setting this bit enables the soft start function for the SR signals.
Table 85. Register 0x55—SR2 Rising Edge Timing (SR2 Pin)
Bits Bit Name R/W Description
[7:0] t
11
R/W This register contains the eight MSBs of the 12-bit t
11
time. This value is always used with the top
four bits of Register 0x56, which contains the four LSBs of the t
11
time. Each LSB corresponds to
5 ns resolution. The entire switching period is divided into 40 ns time steps. If the t
Rx
and t
Fx
of a
PWM edge occur within the same 40 ns time step, the PWM output is 0 V. If the t
Rx
and t
Fx
occur
in different 40 ns time steps, the PWM output is set to the programmed value. The absolute
maximum pulse width is t
PERIOD
− 5 ns. It is recommended that the SR2 rising edge not be set
between 80 ns and 115 ns when using the SR soft start.