Datasheet

Data Sheet ADP1046A
Rev. 0 | Page 7 of 88
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
Measurement Accuracy Factory trimmed at 1 V
10 mV to 160 mV −0.5 +0.5 % FSR
−8 +8 mV
0% to 100% of usable input voltage range −3.0 +3.0 % FSR
−42
+42
mV
Temperature Readings Using
Internal Linearization Scheme
RTD source set to 46 µA (Register 0x11 set to
0xE6); NTC R0 = 100 kΩ, 1%; beta = 4250, 1%;
R
EXT
= 16.5 kΩ, 1%
25°C to 100°C 7 °C
100°C to 125°C 5 °C
OTP
Threshold Accuracy T = 85°C with 100 kΩ||16.5 kΩ −0.9 +0.25 % FSR
−14.4 +4 mV
T = 100°C with 100 kΩ||16.5 kΩ −0.5 +1.1 % FSR
−8 +17.6 mV
Comparator Speed 10.5 ms
OTP Threshold Hysteresis 16 mV
PGOOD1, PGOOD2, SHAREo PINS Open-drain outputs
Output Low Voltage V
OL
0.4 V
PSON, SHAREi PINS Digital inputs
Input Low Voltage V
IL
0.8 V
Input High Voltage V
IH
V
DD
− 0.8 V
Leakage Current 1.0 µA
FLAGIN PIN Digital input
Input Low Voltage V
IL
0.4 V
Input High Voltage V
IH
V
DD
− 0.8 V
Propagation Delay Does not include debounce time (Register
0x0A[3] = 1); flag action set to disable PSU
200 ns
Leakage Current 1.0 µA
GATE PIN
Output Low Voltage V
OL
0.4 V
Output High Voltage V
OH
V
DD
− 0.4 V
SDA/SCL PINS
V
DD
= 3.3 V
Input Low Voltage V
IL
0.8 V
Input High Voltage V
IH
V
DD
− 0.8 V
Output Low Voltage V
OL
0.4 V
Leakage Current 1.0 µA
SERIAL BUS TIMING See Figure 2
Clock Operating Frequency 10 100 400 kHz
Bus-Free Time t
BUF
Between stop and start conditions 1.3 µs
Start Hold Time t
HD;STA
Hold time after (repeated) start condition;
after this period, the first clock is generated
0.6 µs
Start Setup Time t
SU;STA
Repeated start condition setup time 0.6 µs
Stop Setup Time t
SU;STO
0.6 µs
SDA Setup Time t
SU;DAT
100 ns
SDA Hold Time
t
HD;DAT
For readback
125
ns
For write
300
ns
SCL Low Timeout t
TIMEOUT
25 35 ms
SCL Low Period t
LOW
1.3 µs
SCL High Period t
HIGH
0.6 µs
Clock Low Extend Time t
LO;SEXT
25 ms
SCL, SDA Fall Time t
F
20 300 ns
SCL, SDA Rise Time t
R
20 300 ns