Datasheet

Data Sheet ADP1046A
Rev. 0 | Page 69 of 88
Table 78. Register 0x4E—OUTD Rising Edge Setting (OUTD Pin)
Bits Bit Name R/W Description
[7:4] t
7
R/W These bits contain the four LSBs of the 12-bit t
7
time. This value is always used with the eight
bits of Register 0x4D, which contains the eight MSBs of the t
7
time. Each LSB corresponds to
5 ns resolution. The entire switching period is divided into 40 ns time steps. If the t
Rx
and t
Fx
of a
PWM edge occur within the same 40 ns time step, the PWM output is 0 V. If the t
Rx
and t
Fx
occur
in different 40 ns time steps, the PWM output is set to the programmed value. The absolute
maximum pulse width is t
PERIOD
− 5 ns.
3 Modulate enable R/W 1 = PWM modulation acts on the t
7
edge.
0 = no PWM modulation of the t
7
edge.
2 t
7
sign R/W 1 = negative sign. Increase of PWM modulation moves t
7
right.
0 = positive sign. Increase of PWM modulation moves t
7
left.
1 Reserved R/W Reserved.
0 Volt-second balance
source selection
R/W If this bit is set to 1, the OUTD rising edge is selected as the start of the integration period for
volt-second balance.
Table 79. Register 0x4F—OUTD Falling Edge Timing (OUTD Pin)
Bits
Bit Name
R/W
Description
[7:0] t
8
R/W This register contains the eight MSBs of the 12-bit t
8
time. This value is always used with the top
four bits of Register 0x50, which contains the four LSBs of the t
8
time. Each LSB corresponds to
5 ns resolution. The entire switching period is divided into 40 ns time steps. If the t
Rx
and t
Fx
of a
PWM edge occur within the same 40 ns time step, the PWM output is 0 V. If the t
Rx
and t
Fx
occur
in different 40 ns time steps, the PWM output is set to the programmed value. The absolute
maximum pulse width is t
PERIOD
− 5 ns.
Table 80. Register 0x50—OUTD Falling Edge Setting (OUTD Pin)
Bits Bit Name R/W Description
[7:4] t
8
R/W These bits contain the four LSBs of the 12-bit t
8
time. This value is always used with the eight
bits of Register 0x4F, which contains the eight MSBs of the t
8
time. Each LSB corresponds to
5 ns resolution. The entire switching period is divided into 40 ns time steps. If the t
Rx
and t
Fx
of a
PWM edge occur within the same 40 ns time step, the PWM output is 0 V. If the t
Rx
and t
Fx
occur
in different 40 ns time steps, the PWM output is set to the programmed value. The absolute
maximum pulse width is t
PERIOD
− 5 ns.
3 Modulate enable R/W 1 = PWM modulation acts on the t
8
edge.
0 = no PWM modulation of the t
8
edge.
2 t
8
sign R/W 1 = negative sign. Increase of PWM modulation moves t
8
right.
0 = positive sign. Increase of PWM modulation moves t
8
left.
[1:0] Reserved R/W Reserved.
Table 81. Register 0x51—SR1 Rising Edge Timing (SR1 Pin)
Bits Bit Name R/W Description
[7:0] t
9
R/W This register contains the eight MSBs of the 12-bit t
9
time. This value is always used with the top
four bits of Register 0x52, which contains the four LSBs of the t
9
time. Each LSB corresponds to
5 ns resolution. The entire switching period is divided into 40 ns time steps. If the t
Rx
and t
Fx
of a
PWM edge occur within the same 40 ns time step, the PWM output is 0 V. If the t
Rx
and t
Fx
occur
in different 40 ns time steps, the PWM output is set to the programmed value. The absolute
maximum pulse width is t
PERIOD
− 5 ns. It is recommended that the SR1 rising edge not be set
between 80 ns and 115 ns when using the SR soft start.