Datasheet

Data Sheet ADP1046A
Rev. 0 | Page 67 of 88
Table 69. Register 0x45—OUTB Rising Edge Timing (OUTB Pin)
Bits Bit Name R/W Description
[7:0] t
3
R/W This register contains the eight MSBs of the 12-bit t
3
time. This value is always used with the top
four bits of Register 0x46, which contains the four LSBs of the t
3
time. Each LSB corresponds to
5 ns resolution. The entire switching period is divided into 40 ns time steps. If the t
Rx
and t
Fx
of a
PWM edge occur within the same 40 ns time step, the PWM output is 0 V. If the t
Rx
and t
Fx
occur
in different 40 ns time steps, the PWM output is set to the programmed value. The absolute
maximum pulse width is t
PERIOD
− 5 ns.
Table 70. Register 0x46—OUTB Rising Edge Setting (OUTB Pin)
Bits Bit Name R/W Description
[7:4] t
3
R/W These bits contain the four LSBs of the 12-bit t
3
time. This value is always used with the eight
bits of Register 0x45, which contains the eight MSBs of the t
3
time. Each LSB corresponds to
5 ns resolution. The entire switching period is divided into 40 ns time steps. If the t
Rx
and t
Fx
of a
PWM edge occur within the same 40 ns time step, the PWM output is 0 V. If the t
Rx
and t
Fx
occur
in different 40 ns time steps, the PWM output is set to the programmed value. The absolute
maximum pulse width is t
PERIOD
− 5 ns.
3 Modulate enable R/W 1 = PWM modulation acts on the t
3
edge.
0 = no PWM modulation of the t
3
edge.
2
t
3
sign
R/W
1 = negative sign. Increase of PWM modulation moves t
3
right.
0 = positive sign. Increase of PWM modulation moves t
3
left.
1 Reserved R/W Reserved.
0 Volt-second balance
source selection
R/W If this bit is set to 1, the OUTB rising edge is selected as the start of the integration period for
volt-second balance.
Table 71. Register 0x47—OUTB Falling Edge Timing (OUTB Pin)
Bits Bit Name R/W Description
[7:0] t
4
R/W This register contains the eight MSBs of the 12-bit t
4
time. This value is always used with the top
four bits of Register 0x48, which contains the four LSBs of the t
4
time. Each LSB corresponds to
5 ns resolution. The entire switching period is divided into 40 ns time steps. If the t
Rx
and t
Fx
of a
PWM edge occur within the same 40 ns time step, the PWM output is 0 V. If the t
Rx
and t
Fx
occur
in different 40 ns time steps, the PWM output is set to the programmed value. The absolute
maximum pulse width is t
PERIOD
− 5 ns.
Table 72. Register 0x48—OUTB Falling Edge Setting (OUTB Pin)
Bits Bit Name R/W Description
[7:4] t
4
R/W These bits contain the four LSBs of the 12-bit t
4
time. This value is always used with the eight
bits of Register 0x47, which contains the eight MSBs of the t
4
time. Each LSB corresponds to
5 ns resolution. The entire switching period is divided into 40 ns time steps. If the t
Rx
and t
Fx
of a
PWM edge occur within the same 40 ns time step, the PWM output is 0 V. If the t
Rx
and t
Fx
occur
in different 40 ns time steps, the PWM output is set to the programmed value. The absolute
maximum pulse width is t
PERIOD
− 5 ns.
3 Modulate enable R/W 1 = PWM modulation acts on the t
4
edge.
0 = no PWM modulation of the t
4
edge.
2 t
4
sign R/W 1 = negative sign. Increase of PWM modulation moves t
4
right.
0 = positive sign. Increase of PWM modulation moves t
4
left.
[1:0] Reserved R/W Reserved.
Table 73. Register 0x49—OUTC Rising Edge Timing (OUTC Pin)
Bits Bit Name R/W Description
[7:0] t
5
R/W This register contains the eight MSBs of the 12-bit t
5
time. This value is always used with the top
four bits of Register 0x4A, which contains the four LSBs of the t
5
time. Each LSB corresponds to
5 ns resolution. The entire switching period is divided into 40 ns time steps. If the t
Rx
and t
Fx
of a
PWM edge occur within the same 40 ns time step, the PWM output is 0 V. If the t
Rx
and t
Fx
occur
in different 40 ns time steps, the PWM output is set to the programmed value. The absolute
maximum pulse width is t
PERIOD
− 5 ns.