Datasheet

ADP1046A Data Sheet
Rev. 0 | Page 66 of 88
Bits Bit Name R/W Description
[5:0] Switching frequency R/W
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Frequency (kHz)
1 1 0 0 0 1 416.67
1 1 0 0 1 0 446.43
1 1 0 0 1 1 480.77
1 1 0 1 0 0 520.83
1 1 0 1 0 1 568.18
1 1 0 1 1 0 625
1 1 1 1 1 1 Resonant mode
Table 65. Register 0x41OUTA Rising Edge Timing (OUTA Pin)
Bits
Bit Name
R/W
Description
[7:0] t
1
R/W This register contains the eight MSBs of the 12-bit t
1
time. This value is always used with the top
four bits of Register 0x42, which contains the four LSBs of the t
1
time. Each LSB corresponds to
5 ns resolution. The entire switching period is divided into 40 ns time steps. If the t
Rx
and t
Fx
of a
PWM edge occur within the same 40 ns time step, the PWM output is 0 V. If the t
Rx
and t
Fx
occur
in different 40 ns time steps, the PWM output is set to the programmed value. The absolute
maximum pulse width is t
PERIOD
− 5 ns.
Table 66. Register 0x42OUTA Rising Edge Setting (OUTA Pin)
Bits Bit Name R/W Description
[7:4] t
1
R/W These bits contain the four LSBs of the 12-bit t
1
time. This value is always used with the eight
bits of Register 0x41, which contains the eight MSBs of the t
1
time. Each LSB corresponds to
5 ns resolution. The entire switching period is divided into 40 ns time steps. If the t
Rx
and t
Fx
of a
PWM edge occur within the same 40 ns time step, the PWM output is 0 V. If the t
Rx
and t
Fx
occur
in different 40 ns time steps, the PWM output is set to the programmed value. The absolute
maximum pulse width is t
PERIOD
− 5 ns.
3 Modulate enable R/W 1 = PWM modulation acts on the t
1
edge.
0 = no PWM modulation of the t
1
edge.
2 t
1
sign R/W 1 = negative sign. Increase of PWM modulation moves t
1
right.
0 = positive sign. Increase of PWM modulation moves t
1
left.
1 Reserved R/W Reserved.
0 Volt-second balance
source selection
R/W If this bit is set to 1, the OUTA rising edge is selected as the start of the integration period for
volt-second balance.
Table 67. Register 0x43OUTA Falling Edge Timing (OUTA Pin)
Bits Bit Name R/W Description
[7:0] t
2
R/W This register contains the eight MSBs of the 12-bit t
2
time. This value is always used with the top
four bits of Register 0x44, which contains the four LSBs of the t
2
time. Each LSB corresponds to
5 ns resolution. The entire switching period is divided into 40 ns time steps. If the t
Rx
and t
Fx
of a
PWM edge occur within the same 40 ns time step, the PWM output is 0 V. If the t
Rx
and t
Fx
occur
in different 40 ns time steps, the PWM output is set to the programmed value. The absolute
maximum pulse width is t
PERIOD
− 5 ns.
Table 68. Register 0x44OUTA Falling Edge Setting (OUTA Pin)
Bits Bit Name R/W Description
[7:4] t
2
R/W These bits contain the four LSBs of the 12-bit t
2
time. This value is always used with the eight
bits of Register 0x43, which contains the eight MSBs of the t
2
time. Each LSB corresponds to
5 ns resolution. The entire switching period is divided into 40 ns time steps. If the t
Rx
and t
Fx
of a
PWM edge occur within the same 40 ns time step, the PWM output is 0 V. If the t
Rx
and t
Fx
occur
in different 40 ns time steps, the PWM output is set to the programmed value. The absolute
maximum pulse width is t
PERIOD
− 5 ns.
3 Modulate enable R/W 1 = PWM modulation acts on the t
2
edge.
0 = no PWM modulation of the t
2
edge.
2 t
2
sign R/W 1 = negative sign. Increase of PWM modulation moves t
2
right.
0 = positive sign. Increase of PWM modulation moves t
2
left.
[1:0] Reserved R/W Reserved.